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參數(shù)資料
| 型號： | 7805ALPRPFS |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, DFP28 |
| 封裝： | RAD-PAK, LDFP-28 |
| 文件頁數(shù)： | 13/34頁 |
| 文件大?。?/td> | 605K |
| 代理商： | 7805ALPRPFS |
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Memory
PRELIMINARY
20
All data sheets are subject to change without notice
2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
12.19.01 Rev 6
1000583
POWER-UP CONDITIONS (POWER-ON RESET)
When power is applied to the 7805ALP the device powers up in a known condition. The device powers up in system
standby (SSTBY) mode where all DACs in the package are in low power mode, the reference is active and the outputs
of the DACs are connected internally through a high impedance to ground. Figure 16 show the default conditions for
the system control register. Since a write to the system control register is required to remove the standby condition,
relevant default conditions are only applicable for PD and SSTBY in the system control register. The following are the
bits in the channel control register for which default conditions are applicable, STBY, CLR, MX1 and MX0. Figure 17
shows the default conditions for the channel control register.
FIGURE 16. DEFAULT CONDITIONS FOR THE 7805ALP SYSTEM CONTROL REGISTER ON POWER-UP
FIGURE 17. DEFAULT CONDITIONS FOR THE 7805ALP CHANNEL CONTROL REGISTER ON POWER-UP
The flowchart in Figure 18 shows the steps necessary to control the 7805ALP following power-on. This flowchart
details the necessary steps when using the 7805ALP in its 10-bit parallel mode. The first step is to write to the system
control register to clear the SSTBY bit and to configure the part for 10-bit parallel mode and select the required coding
scheme. The next step is to determine whether writing is to the Main or Sub DAC. This is achieved by writing to the
channel control register. Other bits that need to be configured in the channel control register are MX1 and MX0 which
determine the source of the VBIAS for the selected DAC and the channel STBY and channel CLR bits need to be con-
figured as desired. Once writing to the channel control register is complete, data can now be written to the selected
Main or Sub DAC. Parallel data can also be written to the device in 8+2 format to allow interface to 8-bit processors.
Eight-bit mode is invoked by writing a one to the 10/8 bit in the system control register.
When in the 8-bit mode the two unused data bits (DB1 and DB0) are used as hardware control bits and have the same
timing characteristics as the address inputs. DB1 is a don’t care bit when writing to both the system and channel con-
trol registers; DB0 acts as the mode select bit and must be low to enable writing to the system control register and
when high enables access to the channel control register. When in the 8-bit data write mode, DB1 acts as a low byte
and high byte enable, when low data is written to the 8 MSBs of the DAC and when high data is written to the two
LSBs. DB0 acts as a bit to select writing to the Main or Sub DAC. When DB0 is low, writing is to the Main DAC, and
when high, writing is to the Sub DAC data register. In the 8+2 mode the channel control register does not have to be
accessed to switch between writing to the Main and Sub DACs as in the 10-bit parallel
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