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參數資料
| 型號： | 7805ALPRPFS |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, DFP28 |
| 封裝： | RAD-PAK, LDFP-28 |
| 文件頁數： | 6/34頁 |
| 文件大小： | 605K |
| 代理商： | 7805ALPRPFS |
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PRELIMINARY
14
All data sheets are subject to change without notice
2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
12.19.01 Rev 6
1000583
AD7805/AD7809 INTERFACE SECTION
The 7805 is a parallel data input device and contains both control registers and data registers. The system control reg-
ister has global control over all DACs in the package while the channel control register allows control over individual
DACs in the package. Two data registers are also available, one for the 10-bit Main DAC and the second for the 8-bit
Sub DAC. In the parallel mode, CS and WR, in association with the address pins, control the loading of data. Data is
transferred from the data register to the DAC register under the control of the LDAC signal. Only data contained in the
DAC register determines the analog output of any DAC. The timing diagram for 10-bit parallel loading is shown in Fig-
ure 2. The MODE pin on the device determines whether writing is to the data registers or to the control registers.
When MODE is at a logic one, writing is to the data registers. In the next write to the data registers a bit in the channel
control register determines whether the Main DAC or the Sub DAC is addressed. This means that to address either
the Main or the Sub DAC the Main/Sub bit in the control register has to be set appropriately before the data register
write. A logic zero on the mode pin enables writing to the control register. Bit MD0 determines whether writing is to the
system control register or to the addressed channel control register.
Bringing the CLR line low resets the DAC registers to one of two known conditions depending on the coding scheme
selected. The hardware clear affects both the Main and Sub DAC registers. With offset binary coding a clear sets the
output of the Main DAC to the bottom of the transfer function, VBIAS/16. With twos complement coding the output of
the DAC is cleared to midscale which is VBIAS. A hardware clear always clears the output of the Sub DAC to midscale
thus the output of the Sub DAC makes zero contribution to the output of the channel.
FIGURE 10. 7805ALP INTERNAL REGISTERS
相關PDF資料 |
PDF描述 |
|---|---|
| 7805ALPRPDS | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28 |
| 7805ALPRPFB | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, DFP28 |
| 7846RPFE | PARALLEL, WORD INPUT LOADING, 16-BIT DAC, DFP28 |
| 7846RPFB | PARALLEL, WORD INPUT LOADING, 16-BIT DAC, DFP28 |
| 7846RPFS | PARALLEL, WORD INPUT LOADING, 16-BIT DAC, DFP28 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 7805B | 制造商:ESTEK 制造商全稱:ESTEK 功能描述:fixed-voltage monolithic integrated-circuit voltage regulators |
| 7805BTG | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 7805C | 制造商:Semiconductors 功能描述: |
| 7805CT | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 7805CU | 制造商:Semiconductors 功能描述: |
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