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參數資料
| 型號： | 7805ALPRPFS |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, DFP28 |
| 封裝： | RAD-PAK, LDFP-28 |
| 文件頁數： | 7/34頁 |
| 文件大小： | 605K |
| 代理商： | 7805ALPRPFS |
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PRELIMINARY
15
All data sheets are subject to change without notice
2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
12.19.01 Rev 6
1000583
7805ALP CONTROL REGISTERS
Access to the control registers of the 7805ALP is achieved by taking the mode pin to a logic low. The control register
of these DACs are configured as in Figures 11 and 12. There are two control registers associated with the part. Sys-
tem control register which looks after the input coding, data format, power down, system clear and system standby.
The channel control register contains bits that affect the operation of the selected DAC. The external address bits are
used to select the DACs. These registers are eight bits wide and the last two bits are control bits. The mode pin must
be low to have access to the control registers.
FIGURE 11. 7805ALP SYSTEM CONTROL REGISTER CONFIGURATION
FIGURE 12. 7805ALP CHANNEL CONTROL REGISTER CONFIGURATION
The external mode pin must be taken high to allow data to be written to the DAC data registers. Figure 13 shows the
bit allocations when 10-bit parallel operation is selected in the system control register.
FIGURE 13. 7805ALP MAIN DAC DATA REGISTER (TOP) AND SUB DAC DATA REGISTER (BOTTOM) CONFIGURATION
(MODE = 1, 10 /8 = 0)
Figure 14 shows the bit allocations when 8-bit parallel operation is selected in the system control register. DB9 to DB2
are retained as data bits. DB1 acts as a high byte or low byte enable. When DB1 is low, the eight MSBs of the data
word are loaded to the input register. When DB1 is high, the low byte consisting of the two LSBs are loaded to the
input register. DB0 is used to select either the Main or Sub DAC when in the byte mode.
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