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參數資料
| 型號： | 7805ALPRPFS |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, DFP28 |
| 封裝： | RAD-PAK, LDFP-28 |
| 文件頁數： | 24/34頁 |
| 文件大小： | 605K |
| 代理商： | 7805ALPRPFS |
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Memory
PRELIMINARY
30
All data sheets are subject to change without notice
2001 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
7805ALP
12.19.01 Rev 6
1000583
FIGURE 26. PICTORIAL VIEW OF TRANSFER FUNCTION FOR ANY DAC CHANNEL
Grounding and Layout Techniques
To obtain optimum performance from the 7805ALP care should be taken with the layout. Causes for concern would be
feedthrough from the interface bus onto the analog circuitry particularly the reference pins and ground loops. The
board should be designed such that the analog anddigital sections are separated as much as possible. Ground plan-
ing and shielding should be used as much as possible. Digital and analog ground planes should only be joined in one
place to avoid ground loops. The ideal place to join the ground planes is at the analog and digital ground pins of the
DAC. Alternatively a star ground should be established on the board to which all other grounds are returned. Good
decoupling is important in achieving optimum performance. All supplies, analog or digital, should be decoupled with 10
mF tantalum and 0.1 mF ceramic capacitors to their respective grounds, and should be as close as possible to the
pins of the device. The main aim of the bypassing element is to maximize the charge stored in the bypass loop while
simultaneously minimizing the inductance of this loop. Inductance in the loop acts as an impedance to high frequency
transients and results in power supply spiking. By keeping the decoupling as close as possible to the device, the loop
area is kept to a minimum thus reducing the possibility of power supply spikes.
On the 7805ALP the REFOUT pin of the device is located next to the DB9 of the data bus, to reduce the risk of digital
feedthrough and noise being coupled from the digital section onto the reference, the REFOUT pin and any trace con-
nected to it should be shielded with analog ground. To reduce the noise on this reference it should be decoupled with
a 0.01 mF capacitor to analog ground, keeping the capacitor as close as possible to the device. The comp pin which is
the output from the internal VDD/2 reference is located next to VOUTD on the DAC and is sensitive to noise pickup
and feedthrough from the DAC output and thus should be shielded with analog ground to keep this reference point as
quiet as possible. The comp pin should be decoupled both to AVDD and AGND with 1–10 nF ceramic capacitors. The
external REFIN pin should also be shielded with analog ground from the digital pins located next to it.
Reference Settling Time
With the REFOUT on the 7805ALP decoupled with a 0.01 mF capacitor to AGND it takes the REFOUT approximately
2 ms to fully settle after taking the device out of power down. When this capacitor is reduced to 1 nF the settling time
reduces to 150 ms. The size of the capacitor required on the REFOUT depends to a large extent on the layout, if the
REFOUT is well shielded with AGND the size of the capacitor can be reduced thus reducing the settling time for the
reference. The internal VDD/2 reference provided at the comp pin when decoupled with a 1 nF capacitor to both AVDD
and AGND has very fast settling time, typically less than 500 ns.
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