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參數資料
| 型號： | 935269343557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | 28 X 28 MM, 3.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, SOT322-2, MS-022, QFP-160 |
| 文件頁數： | 110/143頁 |
| 文件大小： | 696K |
| 代理商： | 935269343557 |
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2004 Aug 25
69
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
1
17 to 118
(964)
16
1111 1111 1 1 1111 1111
FF, 00
18
3
16
18
2212 2212 2 2 2122 2122
44, BB
32
4
1
1222 2222 1 1 2222 2221
01, FE
32
4
1
...
1
23 to 124
(980)
22
1111 2222 1111
0F, F0
32
4
1
1121 1212 1121
1211 2121 1211
AD, 52
32
4
1
VERTICAL
SCALE
RATIO
YACL
COEFFICIENT
SEQUENCE (EXAMPLE)
CYA; CYB
WEIGHT
SUM
DCGY
BCS
(CONTR. | SAT.)
= X/Y
× 64
7.9.2.6
LPI mode (scaling factor range 1 to 1
2; register
bit YACM = 0)
To preserve the signal quality for slight vertical
downscales (scaling factors 1 to 1
2) Linear Phase
Interpolation (LPI) between consecutive lines is
implemented to generate geometrically correct vertical
output lines. Thus, the new geometric position between
lines N and N + 1 can be calculated.
A new output line is calculated by weighting the samples
‘p’ of lines N and N + 1 with the normalized distance to the
newly calculated position:
p(M) = A
× p(N + 1) + (1 A) × p(N); where A=0to 6364.
With NOL = Number of Output Lines and NIL = Number of
Input Lines the scaler register bits YSCI (scaling
increment) and YP (scaling start phase) have to be set
according to the following equations:
YSCI = INT [1024 × (NIL/(NOL 1)] scaling increment
YPx = INT [YSCI16] scaling start phase (recommended
value).
The vertical start phase offset is defined by
YP
64 (YP=0to 64):
YP = 0: offset = 0 geometrical position of 1st
lineout = 1st linein
YP = 64: offset = 6464 = 1 geometrical position of
1st lineout = 2nd linein.
Finally 3 special modes are to be emphasized:
1. Bypass (YSCI = 0, YP = 64); each lineout is equivalent
to corresponding linein
2. Low-pass (YSCI = 0, YP < 64); e.g. YP = 32: average
value of 2 lines (1 + zh filter)
3. For processing of interlaced input signals the LPI
mode must be used (ACCU mode would cause ‘line
pairing’ problems). The scaling start phase for odd and
even field have to be set to:
YPeven = 32 × YPodd (line 1 = odd)
In modes 1 and 2 the first input line is fed to the output
(without processing), so that the number of output lines
equals the number of input lines.
7.9.2.7
Flip option (Mirror = 1)
For both vertical scaling modes there is a flip option
‘mirroring’ available for input lines with a maximum of
384 pixels. In the case of full screen pictures (e.g.
768
× 576) that have to be flipped, they first have to be
downscaled to 384 pixel/line in the horizontal prescaling
unit and after vertical processing (flipping) they may be
rezoomed to the original 768 pixels/line in the following
VPD.
It should be noted that, when using the flip option, the last
input line can not be displayed at the output.
Fig.21 Calculation of output lines.
handbook, halfpage
MHB107
N
Distance = 1
N
+ 1
I
M
I
A
(1
A)
input lines
new calculated position line
of output line M
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