- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄36340 > 935269343557 (NXP SEMICONDUCTORS) SPECIALTY CONSUMER CIRCUIT, PQFP160 PDF資料下載
參數(shù)資料
| 型號： | 935269343557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | 28 X 28 MM, 3.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, SOT322-2, MS-022, QFP-160 |
| 文件頁數(shù)： | 6/143頁 |
| 文件大小： | 696K |
| 代理商： | 935269343557 |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁
2004 Aug 25
103
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 94 Overview of peak data rates for non-increment (burst) block transfer congurations at 33 MHz PCI clock
Notes
1. These peak data rates could be reached for transfers with large BLOCKLENGTH settings, in a well performing
PCI-bus system with low bus load and an appropriate target system without cycle stretching or interrupts.
2. No cycle stretching by RDY/DTACK possible.
PROTOCOL
MODE
TIMEOUT
VALUE
WORD
WIDTH
FAST
MODE
TRANSFER
DIRECTION
TARGET SIDE
PEAK DATA
RATE
OVERALL
PEAK DATA
RATE(1)
Intel/Motorola(2)
0
16 bit
enabled
R/W
33 Mbytes/s
23.0 Mbytes/s
Intel/Motorola(2)
0
8 bit
enabled
R/W
16.5 Mbytes/s
13.5 Mbytes/s
Intel/Motorola
1
16 bit
enabled
R/W
22 Mbytes/s
17.0 Mbytes/s
Intel/Motorola
3
16 bit
enabled
R/W
13.2 Mbytes/s
11.2 Mbytes/s
Intel/Motorola(2)
0
16 bit
disabled
R/W
22 Mbytes/s
17.0 Mbytes/s
Intel/Motorola
1
16 bit
disabled
R/W
16.5 Mbytes/s
13.5 Mbytes/s
It is possible to halt an actual block transfer by external
interrupt. This is achieved by setting the XIRQ_EN bit in
the DEBI_CONFIG register and asserting the GPIO3 pin
input to LOW while an block transfer is active. If the
XRESUME bit is set to 0, this will end the current block
transfer within the next two Dwords. When XRESUME = 1
the transfer will go to a wait state, but the transfer
operation will not end (DEBI_ACTIVE still asserted). When
GPIO3 is de-asserted to HIGH the block transfer will
resume. The contents of DEBI_AD and DEBI_COMMAND
registers are steadily updated on actual address and block
length values during block transfer. Due to this it is
possible to abort the transfer, read back actual status, do
other transfers and resume later with the saved
information. It should be noted that after a Dword aligned
read block transfer (i.e. if
BLOCKLENGTH [1:0] + A16 [1:0] = 4 or A16 [1:0] = 0) the
read back value of the DEBI_AD register points to the
consecutive address of the just filled PCI memory range.
After a Dword unaligned transfer the read back DEBI_AD
value points 1 Dword further (it should be noted that this
also effects the value of the remaining BLOCKLENGTH
after interrupt; A16 target address read back is not effected
by this). RPS is able to react on the GPIO3 pin events.The
16 AD lines are set to 3-state while DEBI is in XIRQ wait
state (XRESUME enabled). To support target devices of
different endian type the swap register has to be
configured.
Fig.36 Endian swapping.
handbook, full pagewidth
3210
2301
3210
4-byte swap
the four bytes in a double word
are swapped
2-byte swap
the two bytes in a 2-byte word
are swapped
0123
MHB069
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935269481115 | 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5 |
| 935269480115 | 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5 |
| 935269479115 | 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5 |
| 935269476115 | 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5 |
| 935269478115 | 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935269544557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-2US1-V1.3 |
| 935269987557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-1US1-V1.8 SUBBED TO 935269987557 |
| 935270713557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC CHP |
| 935270792551 | 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA |
| 935270792557 | 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。