
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 7: PCI-XIO Module
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
7-2
The PCI-XIO module also includes an XIO interface. The XIO interface “steals PCI
cycle” to run XIO transfers before giving control back to PCI. The XIO interface
supports IDE, NAND and NOR type Flash and Motorola devices, in 8- or 16-bit
datapath.
2.
Functional Description
The Document title variable module supports 33 MHz PCI spec version 2.2. It can
operate as a conguration manager or it can also act as a target to external
conguration cycles when an external processor and north bridge are used in the
system.
Features:
Three base addresses, i.e. apertures, are supported, DRAM, MMIO, XIO.
Option to enable internal PCI system arbiter which can support up to three
external PCI masters.
As a PCI master, it can generate all non-reserved types of single transaction PCI
cycles: IO, memory, interrupt acknowledge and conguration cycle.
Linear burst mode is supported on memory transactions. Other burst mode
transfers are terminated after a single data transfer.
A DMA engine provides high speed transfer to and from SDRAM and an external
PCI device. The DMA can also be used to transfer data to and from XIO devices.
The PCI clock and PCI_RST are generated externally and input to this module.
In PCI terminology it is a single function device.
The following general PCI features are not implemented in the Document title variable
module:
As a PCI target, the device only responds to memory and conguration cycles.
Subtractive decoding is not supported.
There is no hard-coded legacy decoding of address space (such as VGA IO and
memory).
Burst to conguration space is not supported.