
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 15: Audio Output
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
15-12
If an HBE error occurs, the last valid sample or sample pair is repeated until the Audio
Out hardware receives enough data to generate a new serial data frame from the
DMA interface adapter.
3.
Operation
3.1 Clock Programming
3.1.1
Sample Clock Generator
The sample clock generator is programmable to support various sample frequencies.
Figure 6 illustrates the different clock capabilities of the Audio Out unit. A square
wave Direct Digital Synthesizer (DDS) drives the clock system. This DDS is external
to the Audio Out block.
Using the DDS as a clock source allows software to control the coarse and ne clock
rate so that complex forms of synchronization can be implemented without external
hardware. Examples include locking the audio to a broadcast clock, or locking it to an
SPDIF input without changing the system's hardware.
The DDS output is always sent to the OSCLK output pin. This output is intended to be
used as the 256 Fs or 384 Fs system clock source for oversampling D/A converters.
Software may change the oversampling clock frequency dynamically (via the DDS
controls) to adjust the outgoing audio sample rate. In ATSC transport stream
decoding, this is the method used by which the system software locks the audio
output sample rate to the original program provider sample rate.
Figure 6:
Audio Out Clock System and I/O Interface
OSCLK
SCK
WS
SD[0]
SD[1]
SD[2]
SD[3]
(e.g. 256 x Fs)
(e.g. 64 x Fs)
Parallel to Serial
LEFT sample
RIGHT sample
AO_CC[31:0]
Audio Out domain
SER_MASTER
div N+1
WSDIV
SCKDIV
Square Wave
27 MHz x 64
DDS
Converter
32
16 or 32
80
70
DDS from
Clocks Module