
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
21-15
4.
Application Notes
4.0.1
PNX1300 Series versus PNX15xx Series VLD
The MPEG-2 Macroblock Header Output Format now differs in two ways: the
First Forward Motion Vector bit[1] which was unused is now the “First Macro
Block” bit, and the sixth word bits[23:16] now contain the Slice Start Code.
The PNX1300 Series does not implement the “Parse Long” command.
In the VLD_STATUS register, the PNX1300 Series does not implement the
following bits:
– Bit[6] RL Overow
In the VLD_CONTROL register, the PNX1300 Series does not implement the
following bits:
– Bit[16] Slice_strobe
– Bit[15:8] Slice_start_code
– Bit[2] DMA_input_done_mode
In addition, the Little_Endian mode bit is on bit[1] in the PNX1300 Series; but it is
bit[0] in this module.
5.
Register Descriptions
5.1 PNX1300 Series and PNX15xx Series Register Differences
The current VLD is a compatible superset of the VLD that was implemented in the
PNX1300 Series chip. Differences in the register denitions are noted in magenta
text.
The PNX15xx Series implementation removed the RL/MBH write-back DMA
channels. Differences from the current VLD implementation are noted in blue text.
The base address for the PNX15xx Series VLD module is 0x07 5000.
5.2 VLD Register Summary
Table 9:
Register Summary
Offset
Symbol
Description
0x07 5000
VLD_COMMAND
Variable Length Decoder Command
0x07 5004
VLD_SR
VLD Shift Register (shadow)
0x07 5008
VLD_QS
Quantization Scale Code to be output by the VLD
0x07 500C
VPD_PI
VLD Picture Information
0x07 5010
VLD_MC_STATUS
VLD and MC Status register
0x07 5014
VLD_IE
VLD Interrupt Enable
0x07 5018
VLD_CTL
VLD Control register