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參數資料
型號: A3PN125-ZVQG100I
元件分類: FPGA
英文描述: FPGA, 3072 CLBS, 125000 GATES, PQFP100
封裝: 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100
文件頁數: 41/100頁
文件大小: 3284K
代理商: A3PN125-ZVQG100I
ProASIC3 nano DC and Switching Characteristics
Ad vance v0.2
2-31
Timing Characteristics
Table 2-48 1.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.60
13.17
0.04
1.52
TBD
0.43
11.64
10.91
2.81
2.67
ns
–1
0.51
11.20
0.04
1.29
TBD
0.36
9.90
9.28
2.39
2.27
ns
–2
0.45
9.83
0.03
1.14
TBD
0.32
8.69
8.15
2.10
1.99
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating
values.
Table 2-49 1.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.60
8.10
0.04
1.52
TBD
0.43
5.78
6.45
2.80
2.79
ns
–1
0.51
6.89
0.04
1.29
TBD
0.36
4.92
5.48
2.39
2.37
ns
–2
0.45
6.05
0.03
1.14
TBD
0.32
4.32
4.81
2.09
2.08
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating
values.
Table 2-50 1.5 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.60
8.87
0.04
1.52
2.14
0.43
8.06
7.19
2.81
2.67
ns
–1
0.51
7.54
0.04
1.29
1.82
0.36
6.86
6.12
2.39
2.27
ns
–2
0.45
6.62
0.03
1.14
1.60
0.32
6.02
5.37
2.10
1.99
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating
values.
Table 2-51 1.5 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.60
4.04
0.04
1.52
2.14
0.43
3.50
3.11
2.80
2.79
ns
–1
0.51
3.44
0.04
1.29
1.82
0.36
2.98
2.65
2.39
2.37
ns
–2
0.45
3.02
0.03
1.14
1.60
0.32
2.62
2.32
2.09
2.08
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating
values.
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A3PN125-ZVQG100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
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相關代理商/技術參數
參數描述
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