- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374047 > AD7183 (Analog Devices, Inc.) Advanced Video Decoder with 10-Bit ADC and Component Input Support PDF資料下載
參數(shù)資料
| 型號： | AD7183 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
| 中文描述： | 先進(jìn)的視頻解碼器，10位ADC和組件輸入支持 |
| 文件頁數(shù)： | 17/41頁 |
| 文件大小： | 484K |
| 代理商： | AD7183 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
REV. 0
ADV7183
–17–
Control and Pixel Interface FIFO Modes
When the ADV7183 is configured to operate in this mode, pixel
data generated within the part is buffered by a 512-pixel deep
FIFO. Only active video pixels and control codes are written into
the FIFO; the others have been dropped. In this mode the output
is operating asynchronously and a CLKIN must be provided to
clock pixels out of the FIFO. The CLKIN must operate faster than
the effective data transfer rate into the FIFO. This rate will be
determined by the number of active pixels per line. If the CLKIN
is not above this, the FIFO may overflow. The ADV7183 controls
the FIFO when set to operate in SCAPI mode. DV (data valid) is
internally fed back to the RD (read enable), unlike the synchronous
pixel mode where DV will not indicate the validity of the current
pixel and only acts as an indication of how much data is stored in
the FIFO. DV will go high at the same time as AFF and remain
high until the FIFO is empty.
By internally setting DV to RD the system ensures that the FIFO
never overflows. When using this mode the status of data on the
pixel outputs can be determined by two indicators, DV and QCLK.
DV will go active two clock cycles (LLC1) before valid data appears
on the bus. QCLK is a qualified clock derived from CLKIN, but
will only be present when valid pixel data is output from the FIFO.
DV indicates valid pixel or control code data. Using these two
control signals, the user can differentiate between pixel information
and invalid data. Figure 25 shows the basic timing relationship
for this mode.
The operation of the ADV7183 in CAPI mode is similar to that
of SCAPI mode with the exception that now the FIFO is con-
trolled by the system; the system must monitor the almost full
flag (AFF), the almost empty flag (AEF), and control the FIFO
read enable (RD). Unlike SCAPI mode, the QCLK is not gated
and is therefore continuous. Figure 26 shows the basic timing
relationship of this mode.
PIXEL DATA
DV
CLKIN
QCLK
AFF
AEF
NOTE
THE POLARITY OF AFF AND AEF ARE CONTROLLED BY THE PFF BIT.
DV POLARITY IS SET BY THE PDV BIT.
Figure 25. SCAPI Output Mode FIFO Operation
RD
CLKIN
QCLK
AFF
AEF
NOTE
THE POLARITY OF AFF AND AEF ARE CONTROLLED BY THE PFF BIT.
DATA
Figure 26. CAPI Output Mode FIFO Operation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7185 | Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
| ADV7185KST | Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
| ADV7190KST | Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs |
| ADV7191 | Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs |
| ADV7191KST | Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7190 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4.8 kHz Ultra-Low Noise 24-Bit Sigma-Delta ADC with PGA |
| AD7190_08 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4.8 kHz Ultralow Noise 24-Bit Sigma-Delta ADC with PGA |
| AD7190BRUZ | 功能描述:IC ADC 2CH 24BIT W/PGA 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7190BRUZ | 制造商:Analog Devices 功能描述:IC, ADC, 24BIT, 4.8KSPS, TSSOP-24 |
| AD7190BRUZ-REEL | 功能描述:IC ADC 2CH 24BIT W/PGA 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。