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參數資料
| 型號： | AD7183 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
| 中文描述： | 先進的視頻解碼器，10位ADC和組件輸入支持 |
| 文件頁數： | 26/41頁 |
| 文件大小： | 484K |
| 代理商： | AD7183 |
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REV. 0
–26–
ADV7183
Table XVIII. Temporal Decimation Register (Subaddress 0E)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
TDE
1
0
1
Disabled
Enabled
Suppress Frames; Start with Even Field
Suppress Frames; Start with Odd Field
Suppress Even Fields Only
Suppress Odd Fields Only
Skip None
Skip 1 Field/Frame
Skip 2 Fields/Frames
Skip 3 Fields/Frames
Skip 4 Fields/Frames
Skip 5 Fields/Frames
Skip 6 Fields/Frames
Skip 7 Fields/Frames
Skip 8 Fields/Frames
Skip 9 Fields/Frames
Skip 10 Fields/Frames
Skip 11 Fields/Frames
Skip 12 Fields/Frames
Skip 13 Fields/Frames
Skip 14 Fields/Frames
Skip 15 Fields/Frames
Set to Zero
TDC[1:0]
2
0
0
1
1
0
1
0
1
TDR[3:0]
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RESERVED
NOTES
1
Temporal Decimation Enable. Allows the user to enable/disable the temporal function. Configured using TDC[1:0] and TDR[3:0].
2
Temporal Decimation Control. Allows the user to select the suppression of selected fields of video.
3
Temporal Decimation Rate. Specifies how many fields/frames to be skipped before a valid one is output. As specified in the TDC[1:0] register.
0
Table XIX. Power Management Register (Subaddress 0F)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
PSC[1:0]
1
0
0
1
1
0
1
0
1
Full Operation
CVBS Input Only
Digital Only
Power Save Mode
Power-Down Controller by Pin
Power-Down Controller by Bit
Reference Functional
Reference in Power Save Mode
Clock Generator Functional
CG in Power Save Mode
System Functional
Power-Down
Normal Operation
Require Video Signal
PDBP
2
0
1
PS_REF
3
0
1
PS_CG
4
0
1
PWRDN
5
0
1
TRAQ
6
0
1
RESET
7
0
1
Resets Digital Core and I
2
C
NOTES
1
Power Save Control. Allows a set of different power save modes to be selected.
2
Power Down Bit Priority. There are two ways to shut down the digital core; the Power-Down Bit sets which has higher priority.
3
Power Save Reference. Allows the user to enable/disable the internal analog reference.
4
Power Save for the LLC Clock Generator
5
Power Down. Disables the input pads and powers down the 27 MHz clock.
6
Timing Reacquire. Will cause the part to reaquire the video signal and is the software version of the ISO pin. If bit is set will clear itself on the next 27 MHz clock
cycle.
7
Resets Digital Core and I
2
C self-clearing bit.
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