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| 型號(hào)： | AD7183 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
| 中文描述： | 先進(jìn)的視頻解碼器，10位ADC和組件輸入支持 |
| 文件頁(yè)數(shù)： | 9/41頁(yè) |
| 文件大小： | 484K |
| 代理商： | AD7183 |
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ADV7183
–9–
(FEATURES continued from page 1)
CCIR/Square Pixel Operation
Integrated On-Chip Video Timing Generator
Synchronous or Asynchronous Output Timing
Line-Locked Clock Output
Closed Captioning Passthrough Operation
Vertical Blanking Interval Support
Power-Down Mode
2-Wire Serial MPU Interface (I
2
C-Compatible)
5 V Analog 3.3 V Digital Supply Operation
80-Lead LQFP Package
GENERAL DESCRIPTION
The ADV7183 is an integrated video decoder that automatically
detects and converts a standard analog baseband television sig-
nal compatible with worldwide standards NTSC or PAL into
4:2:2 or 4:1:1 component video data compatible with 16-/8-bit
CCIR601/CCIR656.
The advanced and highly flexible digital output interface
enables performance video decoding and conversion in both
frame-buffer-based and line-locked clock-based systems. This
makes the device ideally suited for a broad range of applica-
tions with diverse analog video characteristics, including
tape-based sources, broadcast sources, security/surveillance
cameras, and professional systems.
Fully integrated line stores enable real-time horizontal and
vertical scaling of captured video down to icon size. The 10-bit
accurate A/D conversion provides professional quality SNR
performance. This allows true 8-bit resolution in the 8-bit out-
put mode.
The six analog input channels accept standard composite,
S-video, and component YCrCb video signals in an extensive
number of combinations. AGC and clamp restore circuitry
allow an input video signal peak-to-peak range of 0.5 V up to
2 V. Alternatively, these can be bypassed for manual settings.
The fixed 27 MHz clocking of the ADCs and data path for all
modes allows very precise and accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line-locked even with
±
5% line length varia-
tion. The output control signals allow glueless interface
connection in almost any application.
The ADV7183 modes are set up over a 2-wire serial bidirec-
tional port (I
2
C-compatible).
The ADV7183 is fabricated in a 5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with
lower power dissipation.
The ADV7183 is packaged in a small 80-pin LQFP package.
ANALOG INPUT PROCESSING
The ADV7183 has six analog video input channels. These six
channels can be arranged in a variety of configurations to support
up to six CVBS input signals, three S-video input signals, and two
YCrCb component analog video input signals. The INSEL[3:0]
bits control the input type and channel selected.
The analog
front end includes three clamp circuits for DC restore.
There are
three sample-and-hold amplifiers prior to the ADC which are
used to enable simultaneous sampling of up to three channels in
a YCrCb input mode. Two 10-bit ADCs are used for sampling.
The entire analog front end is fully differential which ensures that
the video is captured to the highest quality possible. This is very
important in highly integrated systems such as video decoders.
Figure 5 shows the analog front end section of the ADV7183.
CLAMP V
1
CLAMP U
1
MUX 6CVBS 3YC 2YUV
SHA
2
SHA
2
SHA
2
MUX
Y ADC
2
C ADC
2
NOTES
ANALOG SIGNAL PATH KEPT FULLY DIFFERENTIAL
ADCs: 10-BIT ACCURATE; 12dB GAIN RANGE
CLAMP BLOCKS CONTAIN A SET OF CURRENT SOURCES FOR DC
RESTORATION; U AND V HAVE ONLY HALF BANDWIDTH (SAMPLED
SIMULTANEOUSLY, CONVERTED SEQUENTIALLY)
PIPELINED
10
10
CLAMP Y
1
Figure 5. Analog Front End Block Diagram
CLAMPING
The clamp control on the ADV7183 consists of a digitally
controlled analog current and voltage clamp and a digitally
controlled digital clamp circuit. The coupling capacitor on each
channel is used to store and filter the clamping voltage. A digital
controller controls the clamp up and down current sources that
charge the capacitor on every line. Four current sources are
used in the current clamp control, two large current sources are
used for coarse clamping, and two small current sources are used
for fine clamping. The voltage clamp, if enabled, is only used on
startup or if a channel is switched. This clamp pulls the video
into the midrange of the ADC, which results in faster clamping
and faster lock-in time for the decoder. The fourth clamp con-
troller is fully digital and clamps the ADC output data, which
results in extremely accurate clamping. It also has the added
advantage of being fully digital, which results in very fast clamp
timing and makes the entire clamping process very robust in
terms of handling large amounts of hum that can be present on
real-world video signals.
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