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| 型號： | AD7641ACP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 18-Bit, 2 MSPS SAR ADC |
| 中文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC48 |
| 封裝： | MO-220-VKKD, LFCSP-48 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大小： | 324K |
| 代理商： | AD7641ACP |
AD7641
Preliminary Technical Data
POWER SUPPLY
The AD7641 uses three sets of power supply pins: an analog 2.5
V supply AVDD, a digital 2.5 V core supply DVDD, and a digital
input/output interface supply OVDD. The OVDD supply allows
direct interface with any logic working between 2.3 V and 5.25
V. To reduce the number of supplies needed, the digital core
(DVDD) can be supplied through a simple RC filter from the
analog supply as shown in Figure 7. The AD7641 is independent
of power supply sequencing and thus free from supply voltage
induced latchup. Additionally, it is very insensitive to power
supply variations over a wide frequency range as shown in
Figure 12.
Rev. Pr E | Page 16 of 24
Figure 12. PSRR vs. Frequency
CONVERSION CONTROL
Figure 13 shows the detailed timing diagrams of the conversion
process. The AD7641 is controlled by the signal CNVST which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. The CNVST signal operates independently of CS
and RD signals.
CNVST
BUSY
MODE
t2
t1
t3
t4
t5
t6
t7
t8
ACQUIRE
CONVERT
ACQUIRE
CONVERT
Figure 13. Basic Conversion Timing
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels, with minimum
overshoot and undershoot or ringing.
For applications where the SNR is critical, the CNVST signal
should have a very low jitter. Some solutions to achieve that are
to use a dedicated oscillator for CNVST generation or, at least,
to clock it with a high frequency low jitter clock as shown in
Figure 7.
t9
t8
RESET
DATA
BUS
BUSY
CNVST
Figure 14. RESET Timing
相關(guān)PDF資料 |
PDF描述 |
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| AD7641ACPRL | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| AD7641AST | 18-Bit, 2 MSPS SAR ADC |
| AD7641ASTRL | 18-Bit, 2 MSPS SAR ADC |
| AD7650 | 16-Bit 1 MSPS SAR Unipolar ADC with Ref |
| AD7651 | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:D38999 Series III; No. of Contacts:4; Connector Shell Size:13; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7641ACPRL | 制造商:Analog Devices 功能描述:ADC SGL SAR 2MSPS 18BIT PARALLEL/SERL 48LFCSP - Tape and Reel |
| AD7641AST | 制造商:Analog Devices 功能描述:ADC SGL SAR 2MSPS 18BIT PARALLEL/SERL 48LQFP - Bulk |
| AD7641ASTRL | 制造商:Analog Devices 功能描述:ADC SGL SAR 2MSPS 18BIT PARALLEL/SERL 48LQFP - Tape and Reel |
| AD7641BCPZ | 功能描述:IC ADC 18BIT 2MSPS SAR 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7641BCPZRL | 功能描述:IC ADC 18BIT 2MSPS SAR 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
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