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| 型號： | AD7641ACP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 18-Bit, 2 MSPS SAR ADC |
| 中文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC48 |
| 封裝： | MO-220-VKKD, LFCSP-48 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大小： | 324K |
| 代理商： | AD7641ACP |
AD7641
Preliminary Technical Data
Pin No.
13
Rev. Pr E | Page 8 of 24
Mnemonic
D6 or
EXT/INT
Type
1
DI/O
Description
In all modes except MODE=3, this output is used as Bit 6 of the Parallel Port Data Ouput Bus.
When MODE=3 (serial mode), this input, part of the serial port, is used as a digital select input for
choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected
on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock
signal connected to the SCLK input.
In all modes except MODE=3, this output is used as Bit 7 of the Parallel Port Data Output Bus.
When MODE=3 (serial mode), this input, part of the serial port, is used to select the active state of the
SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
In all modes except MODE=3, this output is used as Bit 8 of the Parallel Port Data Output Bus.
When MODE=3 (serial mode), this input, part of the serial port, is used to invert the SCLK signal. It is
active in both master and slave mode.
In all modes except MODE=3, this output is used as Bit 9 of the Parallel Port Data Output Bus.
When MODE=3 (serial mode), this input, part of the serial port, is used as either an external data input
or a read mode selection input depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy chain the conversion results
from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT
with a delay of 18 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is
output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output SDOUT only
when the conversion is complete.
Input/Output Interface Digital Power Ground.
Input/Output Interface Digital Power. Nominally at the same supply than the supply of the host
interface (2.5 V or 3 V).
Digital Power. Nominally at 2.5 V.
Digital Power Ground.
In all modes except MODE=3, this output is used as Bit 10 of the Parallel Port Data Output Bus.
When MODE=3 (serial mode), this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip shift register. The AD7641 provides
the conversion result, MSB first, from its internal shift register. The data format is determined by the
logical level of OB/2C.
In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK.
In serial mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
In all modes except MODE=3, this putput is used as the Bit 11 of the Parallel Port Data Output Bus.
When MODE=3 (serial mode), this pin, part of the serial port, is used as a serial data clock input or
output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is
updated depends upon the logic state of the INVSCLK pin.
In all modes except MODE=3, this output is used as the Bit 12 of the Parallel Port Data Output Bus.
When MODE=3 (serial mode), this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid.
When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while
SDOUT output is valid.
In all modes except MODE=3, this output is used as the Bit 12 of the Parallel Port Data Output Bus.
In MODE=3 (serial mode) and when EXT/INT is HIGH, this output, part of the serial port, is used as a
incomplete read error flag. In slave mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed high.
Bit 14 to Bit 17 of the Parallel Port Data output bus. These pins are always outputs regardless of the
interface mode.
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the conversion is
complete and the data is latched into the on-chip shift register.
The falling edge of BUSY could be used as a data ready clock signal.
Must be tied to digital ground.
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock.
14
D7or
INVSYNC
DI/O
15
D8 or
INVSCLK
DI/O
16
D9 or
RDC/SDIN
DI/O
17
18
OGND
OVDD
P
P
19
20
21
DVDD
DGND
D10 or
SDOUT
P
P
DO
22
D11 or
SCLK
DI/O
23
D12 or
SYNC
DO
24
D13 or
RDERROR
DO
25-28
D[14:17]
DO
29
BUSY
DO
30
31
32
DGND
RD
CS
P
DI
DI
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