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參數(shù)資料
| 型號： | AD7671 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit 1 MSPS SAR Unipolar ADC with Ref |
| 中文描述： | 16位1 MSPS的特區(qū)單極型ADC檔 |
| 文件頁數(shù)： | 17/23頁 |
| 文件大小： | 336K |
| 代理商： | AD7671 |
REV. PrA
PRELIMINARY TECHNICAL DATA
AD7667
–17–
parallel interface. T he serial interface is multiplexed on
the parallel data bus. T he AD7667 digital interface also
accommodates both 3 V or 5 V logic by simply connecting
the OVDD supply pin of the AD7667 to the host system
interface digital supply. Finally, by using the OB/
2C
in-
put pin, both two’s complement or straight binary coding
can be used.
T he two signals
CS
and
RD
control the interface.
CS
and
RD
have a similar effect because they are OR’d together inter-
nally. When at least one of these signals is high, the interface
outputs are in high impedance. Usually,
CS
allows the selec-
tion of each AD7667 in multicircuits applications and is held
low in a single AD7667 design.
RD
is generally used to
enable the conversion result on the data bus.
t
3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
t
28
t
29
t
14
t
18
t
19
t
20
t
21
t
24
t
26
t
27
t
23
t
22
t
16
t
15
1
2
3
14
15
16
D15
D14
D2
D1
D0
X
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t
25
t
30
Figure 16. Master Serial Data Timing for Reading (Read After Convert)
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
t
3
t
1
t
17
t
14
t
19
t
20
t
21
t
24
t
26
t
25
t
27
t
23
t
22
t
16
t
15
D15
D14
D2
D1
D0
X
1
2
3
14
15
16
t
18
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
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| AD7671AST | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LQFP 制造商:Analog Devices 功能描述:IC 16-BIT ADC |
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