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參數資料
| 型號： | AD7671 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit 1 MSPS SAR Unipolar ADC with Ref |
| 中文描述： | 16位1 MSPS的特區單極型ADC檔 |
| 文件頁數： | 19/23頁 |
| 文件大小： | 336K |
| 代理商： | AD7671 |
REV. PrA
PRELIMINARY TECHNICAL DATA
AD7667
–19–
CS
BYTE
Pins D[15:8]
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
t12
t12
t13
Pins D[7:0]
RD
Figure TBD, 8-bit Parallel Interface
t
1
t
3
t
4
CS = 0
CNVST
,
RD
BUSY
PREVIOUS
CONVERSION
t
12
t
13
DATA
BUS
Figure 15. Slave Parallel Data Timing for Reading
(Read During Convert)
SE RIAL INT E RF AC E
T he AD7667 is configured to use the serial interface when
the SER/
PAR
is held high. T he AD7667 outputs 16 bits of
data, MSB first, on the SDOUT pin. T his data is synchro-
nized with the 16 clock pulses provided on SCLK pin. T he
output data is valid on both the rising and falling edge of the
data clock.
MAST E R SE R IAL INT E R F AC E
Internal C lock
T he AD7667 is configured to generate and provide the serial
data clock SCLK when the EX T /
INT
pin is held low. T he
AD7667 also generates a SYNC signal to indicate to the host
when the serial data is valid. T he serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on RDC/
SDIN input, the data can be read after each conversion or
during the following conversion. Figure 16 and Figure 17
show the detailed timing diagrams of these two modes.
Usually, because the AD7667 is used with a fast throughput,
the mode master, read during conversion is the most recom-
mended serial mode when it can be used.
In read-during-conversion mode, the serial clock and data
toggle at appropriate instants which minimize potential
feedthrough between digital activity and the critical conver-
sion decisions.
In read-after-conversion mode, it should be noted that, unlike in
other modes, the signal BUSY returns low after the 16 data bits
are pulsed out and not at the end of the conversion phase which
results in a longer BUSY width.
SLAVE SE RIAL INT E RFACE
E xternal C lock
T he AD7667 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EX T /
INT
pin is
held high. In this mode, several methods can be used to read
the data. T he external serial clock is gated by
CS
. When
CS
and
RD
are both low, the data can be read after each conversion
or during the following conversion. T he external clock can be
either a continuous or discontinuous clock. A discontinuous
clock can be either normally high or normally low when inac-
tive. Figure 18 and Figure 20 show the detailed timing diagrams
of these methods.
While the AD7667 is performing a bit decision, it is impor-
tant that voltage transients not occur on digital input/output
pins or degradation of the conversion result could occur.
T his is particularly important during the second half of the
conversion phase because the AD7667 provides error cor-
rection circuitry that can correct for an improper bit
SDOUT
CS
SCLK
D1
D0
X
D15
D14
D13
1
2
3
14
15
16
t
3
t
35
t
36
t
37
t
31
t
32
t
16
CNVST
BUSY
EXT/INT = 1
INVSCLK = 0
RD = 0
Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
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