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| 型號(hào)： | AD7709BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Port |
| 中文描述： | 4-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | PLASTIC, SOIC-24 |
| 文件頁(yè)數(shù)： | 11/17頁(yè) |
| 文件大小： | 248K |
| 代理商： | AD7709BR |
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AD7709
–11–
REV. PrA J anuary 2001
PRELIMINARY TECHNICAL DATA
SF
Data Update
Rate (Hz)
Input Range
±160mV ±320mV ±640mV ±1.24V
Word
±20mV
±40mV
±80mV
±2.56V
13
105.3
1.50
1.50
1.60
1.75
3.50
4.50
6.70
11.75
69
19.79
0.60
0.65
0.65
0.65
0.65
0.95
1.40
2.30
255
5.35
0.35
0.35
0.37
0.37
0.37
0.51
0.82
1.25
AD C NOISE PE R F OR MANC E
T ables I and II below show the output rms noise and output peak-to-peak resolution in bits (rounded to the nearest
0.5LSB) for some typical output update rates . T he numbers are typical and generated at a differential input voltage of
0V. T he output update rate is selected via the SF7-SF0 bits in the Filter Register. It is important to note that the peak-
to-peak resolution figures represent the resolution for which there will be no code flicker within a six-sigma limit.
T he
output noise comes from two sources. T he first is the electrical noise in the semiconductor devices (device noise) used in
the implementation of the modulator. Secondly, when the analog input is converted into the digital domain, quantization
noise is added. T he device noise is at a low level and is independant of frequency. T he quantization noise starts at an even
lower level but rises rapidly with increasing frequency to become the dominant noise source.T he numbers in the tables are
given for the bipolar input ranges. For the unipolar ranges the rms noise numbers will be the same as the bipolar range
but the peak to peak resolution is now based on half the signal range which effectively means loosing 1 bit of resolution.
T able I. T ypical Output RMS Noise vs. Input Range and Update Rate for AD7709
Output RMS Noise
in μV
SF
Data Update
Rate (Hz)
Input Range
±160mV ±320mV ±640mV ±1.24V
Word
±20mV
±40mV
±80mV
±2.56V
13
105.3
12
13
14
15
15
15.5
16
16
69
19.79
13
14
15
16
16
16
16
16
255
5.35
14
15
16
16
16
16
16
16
T able II. Peak-to-Peak Resolution vs. Input Range and Update Rate for AD7709
Peak-to-Peak Resolution in Bits
A D 7709 ON-C H IP R E GIST E R S
Both the AD7709 is controlled and configured via 4 on-chip registers as shown in figure 4 and described in more detail
in the following section. In the following descriptions,
SE T
implies a logic 1 state and
CLE ARE D
implies a logic 0 state
unless otherwise stated.
0
A1
A0
DIN
DOUT
ADC Data Register
Filter Register
DIN
DOUT
Configuration Register(24-Bits)
DOUT
REGISTER
SELECT
DECODER
Status Register
Comm unications Register
DIN
DIN
DOUT
DOUT
0
OSCPD
STBY
R/W
WEN
Figure 4. AD7709 On-Chip Registers
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