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| 型號(hào)： | AD7709BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Port |
| 中文描述： | 4-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | PLASTIC, SOIC-24 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大小： | 248K |
| 代理商： | AD7709BR |
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AD7709
–13–
REV. PrA J anuary 2001
PRELIMINARY TECHNICAL DATA
Status Register - (A1,A0=0,0; Power-On-Reset = 00Hex):
T he ADC Status Register is an 8-bit read-only register. T o access the ADC Status Register, the user must write to the
Communications Register selecting the next operation to be a read and load bits A1-A0 with 0,0. T able V outlines the
bit designations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in
the Status Register. SR7 denotes the first bit of the data stream. T he number in brackets indicates the power-on/reset
default status of that bit.
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RDY (0)
0(0)
0(0)
0(0)
E RR (0)
0(0)
ST BY (0)
LOCK (0)
T able V. Status Register Bit Designations
Bit
Location
Bit
Mnemonic
Description
SR 7
R D Y
Ready bit for the ADC
Set
when data is transferred to the ADC data register.
T he RDY bit is
cleared
automatically a period of time before the data register is updated with a
new conversion result or after the ADC data register has been read.
SR 6
0
Bit is automatically
cleared
. Reserved for future use
SR 5
0
T his bit is automatically
cleared.
Reserved for future use
SR 4
0
T his bit is automatically
cleared.
Reserved for future use
SR 3
E R R
ADC Error Bit. T his qualifying bit is set at the same at the RDY bit.
When
Set
it indicates that the result written to the ADC data register has been clamped to all
zeros or all ones. Error sources include Overrange and loss of lock.
T his bit is
Cleared
at the same time as the RDY bit.
SR 2
0
T his bit is automatically
cleared.
Reserved for future use
SR 1
ST BY
Standby bit indication.
When
Set
it indicates that the AD7709 is in low power mode.
Cleared
when the ADC is powerd up.
SR 0
L OC K
PLL lock status bit.
T his bit is
SE T
if the PLL has locked onto the 32kHz crystal oscillator clock. T he ADC will
not start conversion till this bit has been set. If the LOCK bit subsequently goes low the ERR
bit will be set.
Configuration Register(CONFIG) :(A1,A0 = 0,1; Power-On-Reset = 000000Hex)
T he CONFIG Register is a 24-bit register from which data can either be read or to which data can be written. T his
register is used to select the input channel and configure the input range, excitation current sources and I/O port.T able
X III outlines the bit designations for this register. CONFIG24 through CONFIG0 indicate the bit location, CONFIG
denoting the bits are in the Configuration Register. CONFIG24 denotes the first bit of the data stream. T he number in
brackets indicates the power-on/reset default status of that bit. A write to the CONFIG register has immediate effect and
does not reset the the ADCs. T hus , if a current source is switched while the ADC is converting the user will have to wait
for the fullsettling time of the sinc^3 filter before getting a fully settled output. T his equates to 4 outputs.
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