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參數(shù)資料
| 型號(hào)： | AD7709BR |
| 廠(chǎng)商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Port |
| 中文描述： | 4-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | PLASTIC, SOIC-24 |
| 文件頁(yè)數(shù)： | 16/17頁(yè) |
| 文件大小： | 248K |
| 代理商： | AD7709BR |
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AD7709
–16–
REV. PrA J anuary 2001
PRELIMINARY TECHNICAL DATA
C ON F IG 2
R N2
Used in conjunction with RN1 and RN0 to select the analog input range.
C ON F IG 1
R N1
Used in conjunction with RN2 and RN0 to select the analog input range.
C ON F IG 0
R N0
Used in conjunction with RN2 and RN1 to select the analog input range.
RN2
0
0
0
0
1
1
1
1
RN1
0
0
1
1
0
0
1
1
RN0
0
1
0
1
0
1
0
1
Selected Main ADC Input Range (Vref=2.5V)
±20mV
±40mV
±80mV
±160mV
±320mV
±640mV
±1.28V
±2.56V
Filter Register:(A1,A0=1,0; Power-On-Reset = 00Hex)
T he Filter Register is an 8-bit register from which data can either be read or to which data can be written. T his register
determines the amount of averaging performed by the sinc filter. T able VII outlines the bit designations for the Filter
Register. FR7 through FR0 indicate the bit location, FR denoting the bits are in the Filter Register. FR7 denotes the
first bit of the data stream. T he number in brackets indicates the power-on/reset default status of that bit. T he number in
this register is used to set the decimation factor and thus the output update rate for the ADCs. T he filter register cannot
be written to by the user while the ADC is active. T he update rate is used for the ADC is calculated as follows :
f
adc
= 1
1
X
f
mod
3 8.SF
Where
:
fadc =
fmod =
SF =
ADC Output Update Rate
Modulator Clock Frequency= 32.768K Hz (Main and Aux ADC)
Decimal Value written to SF Register
F R 7
F R 6
F R 5
F R 4
F R 3
F R 2
F R 1
F R 0
SF 7(0)
SF6(1)
SF 5(0)
SF 4(0)
SF 3(0)
SF 2(1)
SF 1(0)
SF 0(1)
T able VII. Filter Register Bit Designations
T he allowable range for SF is 13dec to 255dec. Examples of SF values and corresponding conversion rate (f
adc
) and time
(t
adc
) are shown in table X II below. It should also be noted that both ADC input channels are chopped to minimise offset
errors. T his means that the time for a single conversion or the time to the first conversion result is 2 X t
adc
.
T able X II. Update Rate Vs SF Word.
ADC Data Result Register (DAT A):(A1,A0=1,1; Power-On-Reset = 000000Hex)
T he conversion result for the selected ADC channel is stored in the ADC data register (DAT A). T his register is 16-bits
wide. T his is a read only register. On completion of a read from this register the RDY bit in the status register is cleared.
SF (dec)
S F (hex)
f
adc
(Hz)
t
adc
(ms)
13
0D
105.3
9.52
69
45
19.79
50.34
255
FF
5.35
186.77
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