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參數資料
| 型號： | AD7709BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit Sigma Delta ADC with Current Sources, Switchable Reference Inputs and I/O Port |
| 中文描述： | 4-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | PLASTIC, SOIC-24 |
| 文件頁數： | 15/17頁 |
| 文件大小： | 248K |
| 代理商： | AD7709BR |
AD7709
–15–
REV. PrA J anuary 2001
PRELIMINARY TECHNICAL DATA
C ON F IG 14
P3D IG
Digital Input Enable
Set
by user to enable P3 as a digital input
Cleared
by user to configure as pin P3/AIN3 as analog input. T he default configuration is
analog input.
C ON F IG 13
P2E N
P2 digital output enable bit.
Set
by user to enable P2 as a regular digital output pin.
Cleared
by user to tristate P2 output.
PSW2 takes presedance over P2EN.
C ON F IG 12
P1E N
P1 digital output enable bit.
Set
by user to enable P1 as a regular digital output pin.
Cleared
by user to tristate P1 output.
PSW1 takes presedance over P1EN.
C ON F IG 11
P4D AT
Digital input port data bit. P4DAT is read only and will return a 0 if P4DIG=0. If P4 is
enabled as a digital input then the read back value indicates the status of pin P4.
C ON F IG 10
P3D AT
Digital input port data bit. P3DAT is read only and will return a 0 if P3DIG=0. If P3 is
enabled as a digital input then the read back value indicates the status of pin P3.
C ON F IG 9
P2D AT
Digital output port data bit. P2 is digital output only. When the port is active as an output
(P2EN=1), then the value written to the this data bit appears at the output port. Reading
P2DAT will return what was last written to the P2DAT bit on the AD7709.
C ON F IG 8
P1D AT
Digital output port data bit. P1 is digital output only. When the port is active as an output
(P1EN=1), then the value written to the this data bit appears at the output port. Reading
P1DAT will return what was last written to the P1DAT bit on the AD7709.
C ON F IG 7
R E F SE L
ADC reference input select.
Cleared
by user to select REFIN1(+) and REFIN1(-) as the ADC reference.
Set
by user to select REFIN2(+) and REFIN2(-) as the ADC reference.
C ON F IG 6
C H 2
ADC Input Channel Selection bit. Used in conjunction with CH1 and CH0 as shown in
the analog input selection table.
C ON F IG 5
C H 1
ADC Input Channel Selection bit. Used in conjunction with CH2 and CH0 as shown in
the analog input selection table.
C ON F IG 4
C H 0
ADC Input Channel Selection bit. Used in conjunction with CH2 and CH2 as shown in
the analog input selection table.
CH2
0
0
0
0
1
1
1
CH1
0
0
1
1
0
0
1
CH0
0
1
0
1
0
1
0
Positive Input
AIN1
AIN2
AIN3
AIN4
AIN1
AIN3
A IN C OM
Negative Input
A IN C OM
A IN C OM
A IN C OM
A IN C OM
AIN2
AIN4
A IN C OM
Buffer
Positive Analog Input
Positive Analog Input
Positive Analog Input
Positive Analog Input
Positive and Negative Analog Inputs
Positive and Negative Analog Inputs
Positive and Negative Analog Inputs
T he final column indicates if the analog inputs are buffered or unbuffered. T his determines the common mode
input range on each input. If the input is unbuffered (AINCOM) the common mode input includes GND.
C ON F IG 3
U N I
Unipolar/Bipolar Operation Selection Bit.
Set
by user to enable unipolar operation with straight binary output coding i.e. zero differ-
ential input will result in 0000hex output and a fullscale differential input will result in
FFFF Hex output.
Cleared
by user to enable pseudo bipolar operation and offset binary coding, negative
fullscale differential input will result in an output code of 0000 Hex, zero differential in-
put will result in an output code of 8000Hex and a positive fullscale differential input will
result in an output code of FFFF Hex.
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