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參數資料
| 型號： | AD7731BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| 中文描述： | 6-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁數： | 14/44頁 |
| 文件大?。?/td> | 411K |
| 代理商： | AD7731BR |
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AD7731
–14–
REV. 0
Bit
Location
Bit
Mnemonic
Description
CR3
CR2-CR0
ZERO
RS2-RS0
A zero
must
be written to this bit to ensure correct operation of the AD7731.
Register Selection Bits. RS2 is the MSB of the three selection bits. T he three bits select to which
one of eight on-chip registers the next read or write operation takes place as shown in T able VIII.
T able VIII. Register Selection
RS2
RS1
RS0
Register
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
Communications Register (Write Operation)
Status Register (Read Operation)
Data Register
Mode Register
Filter Register
No Register Access
Offset Register
Gain Register
T est Register
Status Register (RS2-RS0 = 0, 0, 0); Power-On/Reset Status: CX Hex
T he Status Register is an 8-bit read-only register. T o access the Status Register, the user must write to the Communications Register
selecting either a single-shot read or continuous read mode and load bits RS2, RS1, RS0 with 0, 0, 0. T able IX outlines the bit desig-
nations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 de-
notes the first bit of the data stream. Figure 5 shows a flowchart for reading from the registers on the AD7731. T he number in brackets
indicates the power-on/reset default status of that bit.
T able IX . Status Register
7
R
S
6
R
S
5
R
S
4
R
S
3
R
S
2
R
S
1
R
S
0
R
S
Y
D
R
)
(
Y
D
T
S
)
(
)
(
Y
B
T
S
)
(
F
E
R
O
N
)
X
(
3
S
M
)
X
(
2
S
M
)
X
(
1
S
M
)
X
(
0
S
M
Bit
Location
Bit
Mnemonic
Description
SR7
RDY
Ready Bit. T his bit provides the status of the
RDY
flag from the part. T he status and func-
tion of this bit is the same as the
RDY
output pin. A number of events set the
RDY
bit high
as indicated in T able X VII.
Steady Bit. T his bit is updated when the filter writes a result to the Data Register. If the filter
is in
FAST
Step mode (see Filter Register section), and responding to a step input, the
STDY
bit remains high as the initial conversion results become available. T he
RDY
output
and bit are set low on these initial conversions to indicate that a result is available. However,
if the
STDY
is high, it indicates that the result being provided is not from a fully settled
second-stage FIR filter. When the FIR filter has fully settled, the
STDY
bit will go low coin-
cident with
RDY
. If the part is never placed into its
FAST
Step mode, the
STDY
bit will go
low at the first Data Register read and it is not cleared by subsequent Data Register reads.
A number of events set the
STDY
bit high as indicated in T able X VII.
STDY
is set high
along with
RDY
by all events in the table except a Data Register read.
Standby Bit. T his bit indicates whether the AD7731 is in its Standby Mode or normal mode
of operation. T he part can be placed in its standby mode using the
STANDBY
input pin or
by writing 011 to the MD2 to MD0 bits of the Mode Register. T he power-on/reset status of
this bit is 0 assuming the
STANDBY
pin is high.
No Reference Bit. If the voltage between the REF IN(+) and REF IN(–) pins is below 0.5 V
or either of these inputs is open-circuit, the NOREF bit goes to 1. If NOREF is active on
completion of a conversion, the Data Register is loaded with all 1s. If NOREF is active on
completion of a calibration, updating of the calibration registers is inhibited.
T hese bits are for factory use. T he power-on/reset status of these bits varies depending on the
factory-assigned number.
SR6
STDY
SR5
ST BY
SR4
NOREF
SR3-SR0
MS3-MS0
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