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參數資料
| 型號： | AD7731BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| 中文描述： | 6-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁數： | 15/44頁 |
| 文件大小： | 411K |
| 代理商： | AD7731BR |
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AD7731
–15–
REV. 0
Data Register (RS2-RS0 = 0, 0, 1); Power On/Reset Status: 000000 Hex
T he Data Register on the part is a read-only register that contains the most up-to-date conversion result from the AD7731. Figure 5
shows a flowchart for reading from the registers on the AD7731. T he register can be programmed to be either 16 or 24 bits wide,
determined by the status of the WL bit of the Mode Register. T he
RDY
output and
RDY
bit of the Status Register are set low when
the Data Register is updated. T he
RDY
pin and
RDY
bit will return high once the full contents of the register (either 16 or 24 bits)
have been read. If the Data Register has not been read by the time the next output update occurs, the
RDY
pin and
RDY
bit will go
high for at least 158.5
×
t
CLK IN
indicating when a read from the Data Register should not be initiated to avoid a transfer from the
Data Register as it is being updated. Once the updating of the Data Register has taken place,
RDY
returns low.
If the Communications Register data sets up the part for a write operation to this register, a write operation must actually take place
in order to return the part to where it is expecting a write operation to the Communications Register (the default state of the inter-
face). However, the 16 or 24 bits of data written to the part will be ignored by the AD7731.
Mode Register (RS2-RS0 = 0, 1, 0); Power-On/Reset Status: 0174 Hex
T he Mode Register is a 16-bit register from which data can either be read or to which data can be written. T his register configures
the operating modes of the AD7731, the input range selection, the channel selection and the word length of the Data Register. T ableX
outlines the bit designations for the Mode Register. MR0 through MR15 indicate the bit location, MR denoting the bits are in the
Mode Register. MR15 denotes the first bit of the data stream. T he number in brackets indicates the power-on/reset default status of
that bit. Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the
registers on the part.
T able X . Mode Register
5
1
R
M
4
1
R
M
3
1
R
M
2
1
R
M
1
1
R
M
0
1
R
M
9
R
M
8
R
M
)
(
2
D
M
)
(
1
D
M
)
(
0
D
M
B
)
(
U
/
)
(
N
E
D
)
(
1
D
)
(
0
D
)
(
L
W
7
R
M
6
R
M
5
R
M
4
R
M
3
R
M
2
R
M
1
R
M
0
R
M
)
(
F
E
R
I
H
)
(
2
N
R
)
(
1
N
R
)
(
0
N
R
)
(
O
B
)
(
2
H
C
)
(
1
H
C
)
(
0
H
C
Bit
Location
Bit
Mnemonic
Description
MR15–MR13
MD2–MD0
Mode Bits. T hese three bits determine the mode of operation of the AD7731 as outlined in
T able X I. T he modes are independent, such that writing new mode bits to the Mode Regis-
ter will exit the part from the mode in which it is operating and place it in the new requested
mode immediately after the Mode Register write. T he function of the mode bits is described
in more detail below.
T able X I. Operating Modes
MD2
MD1
MD0
Mode of Operation
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Sync (Idle) Mode
Continuous Conversion Mode
Single Conversion Mode
Power-Down (Standby) Mode
Internal Zero-Scale Calibration
Internal Full-Scale Calibration
System Zero-Scale Calibration
System Full-Scale Calibration
Power-On/Reset Default
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