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參數資料
| 型號： | AD7731BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| 中文描述： | 6-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁數： | 18/44頁 |
| 文件大小： | 411K |
| 代理商： | AD7731BR |
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AD7731
–18–
REV. 0
Bit
Location
Bit
Mnemonic
Description
MR3
BO
Burnout Current Bit. A 1 in this bit activates the burnout currents. When active, the burnout
currents connect to the selected analog input pair, one source current to the AIN(+) input
and one sink current to the AIN(–) input. A 0 in this bit turns off the on-chip burnout
currents.
Channel Select. T hese three bits select a channel either for conversion or for access to cali-
bration coefficients as outlined in T able X III. T here are three pairs of calibration registers on
the part. In fully differential mode, the part has three input channels so each channel has its
own pair of calibration registers. In pseudo-differential mode, the AD7731 has five input
channels with some of the input channel combinations sharing calibration registers. With
CH2, CH1 and CH0 at a logic 1, the part looks at the AIN6 input internally shorted to itself.
T his can be used as a test method to evaluate the noise performance of the part with no ex-
ternal noise sources. In this mode, the AIN6 input should be connected to an external volt-
age within the allowable common-mode range for the part. T he power-on/default status of
these bits is 1, 0, 0.
MR2–MR0
CH2–CH0
T able X III. Channel Selection
CH2
CH1
CH0 AIN(+)
AIN(–) T ype
Calibration Register Pair
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AIN1
AIN2
AIN3
AIN4
AIN1
AIN3
AIN5
AIN6
AIN6
AIN6
AIN6
AIN6
AIN2
AIN4
AIN6
AIN6
Pseudo Differential
Pseudo Differential
Pseudo Differential
Pseudo Differential
Fully Differential
Fully Differential
Fully Differential
T est Mode
Register Pair 0
Register Pair 1
Register Pair 2
Register Pair 2
Register Pair 0
Register Pair 1
Register Pair 2
Register Pair 2
Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 2002 Hex
T he Filter Register is a 16-bit register from which data can either be read or to which data can be written. T his register determines
the amount of averaging performed by the filter and the mode of operation of the filter. It also sets the chopping mode. T able X IV
outlines the bit designations for the Filter Register. FR0 through FR15 indicate the bit location, FR denoting the bits are in the Filter
Register. FR15 denotes the first bit of the data stream. T he number in brackets indicates the power-on/reset default status of that bit.
Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the registers
on the part.
T able X IV. Filter Register
5
1
R
F
4
1
R
F
3
1
R
F
2
1
R
F
1
1
R
F
0
1
R
F
9
R
F
8
R
F
)
(
1
1
F
S
)
(
0
1
F
S
)
(
9
F
S
)
(
8
F
S
)
(
7
F
S
)
(
6
F
S
)
(
5
F
S
)
(
4
F
S
7
R
F
6
R
F
5
R
F
4
R
F
3
R
F
2
R
F
1
R
F
0
R
F
)
(
3
F
S
)
(
2
F
S
)
(
1
F
S
)
(
0
F
S
)
(
O
R
E
Z
)
(
P
H
C
)
(
P
I
K
S
)
(
T
S
A
F
Bit
Location
Bit
Mnemonic
Description
FR15–FR4
SF11–SF0
Sinc
3
Filter Selection Bits. T he AD7731 contains two filters, a Sinc
3
filter and an FIR filter.
T he 12 bits programmed to SF11 through SF0 sets the amount of averaging which the Sinc
3
filter performs. As a result, the number programmed to these 12 bits affects the –3 dB fre-
quency and output update rate from the part (see Filter Architecture section). T he allowable
range for SF words depends on whether the part is operated with CHP on or off and SK IP
on or off. T able X V outlines the SF ranges for different setups.
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