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參數資料
| 型號： | AD7839 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Octal 13-Bit, Parallel Input, Voltage-Output DAC |
| 中文描述： | 八路13位，并行輸入，電壓輸出DAC |
| 文件頁數： | 9/12頁 |
| 文件大小： | 153K |
| 代理商： | AD7839 |
AD7839
–9–
REV. 0
Power-On with
CLR
Low
The output stage of the AD7839 has been designed to allow
output stability during power-on. If
CLR
is kept low during
power-on, then just after power is applied to the AD7839, the
situation is as depicted in Figure 14. G
1
, G
4
and G
6
are open
while G
2
, G
3
and G
5
are closed.
G
1
G
2
G
4
G
3
G
6
G
5
DUTGND
V
OUT
R
R
14k
V
DAC
Figure 14. Output Stage with V
DD
< 7 V or V
SS
> –3 V;
CLR
Low
V
OUT
is kept within a few hundred millivolts of DUTGND via
G
5
and a 14 k
resistor. This thin-film resistor is connected in
parallel with the gain resistors of the output amplifier. The
output amplifier is connected as a unity gain buffer via G
3
, and
the DUTGND voltage is applied to the buffer input via G
2
. The
amplifier’s output is thus at the same voltage as the DUTGND
pin. The output stage remains configured as in Figure 14 until
the voltage at V
DD
exceeds 7 V and V
SS
is more negative than
–3 V. By now the output amplifier has enough headroom to
handle signals at its input and has also had time to settle. The
internal power-on circuitry opens G
3
and G
5
and closes G
4
and
G
6
. This situation is shown in Figure 15. Now the output ampli-
fier is configured in its noise gain configuration via G
4
and G
6
.
The DUTGND voltage is still connected to the noninverting
input via G
2
and this voltage appears at V
OUT
.
G
1
G
2
G
4
G
3
G
6
G
5
DUTGND
V
OUT
R
R
14k
V
DAC
Figure 15.Output Stage with V
DD
> 7 V and V
SS
< –3 V;
CLR
Low
V
OUT
has been disconnected from the DUTGND pin by the
opening of G
5
, but will track the voltage present at DUTGND
via the configuration shown in Figure 15.
When
CLR
is taken back high, the output stage is configured as
shown in Figure 16. The internal control logic closes G
1
and
opens G
2
. The output amplifier is connected in a noninverting
gain-of-two configuration. The voltage that appears on the V
OUT
pins is determined by the data present in the DAC registers.
G
1
G
2
G
4
G
3
G
6
G
5
DUTGND
V
OUT
R
R
14k
V
DAC
Figure 16. Output Stage After
CLR
Is Taken High
Power-On with
CLR
High
If
CLR
is high on the application of power to the device, the
output stages of the AD7839 are configured as in Figure 17
while V
DD
is less than 7 V and V
SS
is more positive than –3 V.
G
1
is closed and G
2
is open, thereby connecting the output of the
DAC to the input of its output amplifier. G
3
and G
5
are closed
while G
4
and G
6
are open, thus connecting the output amplifier as
a unity gain buffer. V
OUT
is connected to DUTGND via G
5
through a 14 k
resistor until V
DD
exceeds 7 V and V
SS
is more
negative than –3 V.
G
1
G
2
G
4
G
3
G
6
G
5
DUTGND
V
OUT
R
R
14k
V
DAC
Figure 17. Output Stage Powering Up with
CLR
High
While V
DD
< 7 V or V
SS
> –3 V
When the difference between the supply voltages reaches +10 V,
the internal power-on circuitry opens G
3
and G
5
and closes G
4
and G
6
configuring the output stage as shown in Figure 18.
G
1
G
2
G
4
G
3
G
6
G
5
DUTGND
V
OUT
R
R
14k
V
DAC
Figure 18.Output Stage Powering Up with
CLR
High;
V
DD
> 7 V and V
SS
< –3 V
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