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參數(shù)資料
| 型號： | AD7851 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit 333 kSPS Serial A/D Converter |
| 中文描述： | 14位333 kSPS的串行A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 21/36頁 |
| 文件大小： | 435K |
| 代理商： | AD7851 |
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–21–
REV. A
AD7851
SYSTEM OFFSET
CALIBRATION
SYS OFFSET
AGND
V
REF
– 1LSB
MAX SYSTEM OFFSET
IS
±
5% OF V
REF
MAX SYSTEM FULL SCALE
IS
±
2.5% FROM V
REF
ANALOG
INPUT
RANGE
V
REF
– 1LSB
ANALOG
INPUT
RANGE
SYS OFFSET
AGND
MAX SYSTEM OFFSET
IS
±
5% OF V
REF
V
REF
+ SYS OFFSET
Figure 28. System Offset Calibration
Figure 29 shows a system gain calibration (assuming a system
full scale greater than the reference voltage) where the analog
input range has been increased after the system gain calibration
is completed. A system full-scale voltage less than the reference
voltage may also be accounted for a by a system gain calibration.
SYSTEM GAIN
CALIBRATION
V
REF
– 1LSB
AGND
MAX SYSTEM FULL SCALE
IS
±
2.5% FROM V
REF
ANALOG
INPUT
RANGE
V
REF
– 1LSB
ANALOG
INPUT
RANGE
AGND
SYS FULL S.
SYS FULL S.
MAX SYSTEM FULL SCALE
IS
±
2.5% FROM V
REF
Figure 29. System Gain Calibration
Finally in Figure 30 both the system offset and gain are accounted
for by the system offset followed by a system gain calibration.
First the analog input range is shifted upwards by the positive
system offset and then the analog input range is adjusted at the
top end to account for the system full scale.
SYSTEM OFFSET
CALIBRATION
FOLLOWED BY
SYSTEM GAIN
CALIBRATION
SYS OFFSET
AGND
V
REF
– 1LSB
MAX SYSTEM OFFSET
IS
±
5% OF V
REF
MAX SYSTEM FULL SCALE
IS
±
2.5% FROM V
REF
ANALOG
INPUT
RANGE
V
REF
– 1LSB
ANALOG
INPUT
RANGE
SYS OFFSET
AGND
MAX SYSTEM OFFSET
IS
±
5% OF V
REF
V
REF
+ SYS OFFSET
SYS F.S.
MAX SYSTEM FULL SCALE
IS
±
2.5% FROM V
REF
SYS F.S.
Figure 30. System (Gain + Offset) Calibration
Self-Calibration T iming
T he diagram of Figure 27 shows the timing for a full self-
calibration. Here the BUSY line stays high for the full length of
the self-calibration. A self-calibration is initiated by bringing the
CAL
pin low (which initiates an internal reset) and then high
again or by writing to the control register and setting the
ST CAL bit to 1 (
note that if the part is in a power-down mode, the
CAL
pulse width must take account of the power-up time
). T he
BUSY line is triggered high from the rising edge of
CAL
(or the
end of the write to the control register if calibration is initiated
in software), and BUSY will go low when the full self-calibration
is complete after a time t
CAL
as shown in Figure 27.
t
1
= 100ns MIN,
t
15
= 2.5
t
CLKIN
MAX,
t
CAL
= 250026
t
CLKIN
CAL
(I/P)
BUSY (O/P)
t
1
t
15
t
CAL
Figure 27. Timing Diagram for Full Self-Calibration
For the self-(gain + offset), self-offset and self-gain calibrations,
the BUSY line will be triggered high by the rising edge of the
CAL
signal (or the end of the write to the control register if cali-
bration is initiated in software) and will stay high for the full du-
ration of the self-calibration. T he length of time that the BUSY
is high for will depend on the type of self-calibration that is initi-
ated. T ypical figures are given in T able IX . T he timing dia-
grams for the other self-calibration options will be similar to that
outlined in Figure 27.
System Calibration Description
System calibration allows the user to take out system errors
external to the AD7851 as well as calibrate the errors of the
AD7851 itself. T he maximum calibration range for the system
offset errors is
±
5% of V
REF
and for the system gain errors is
±
2.5% of V
REF
. T his means that the maximum allowable system
offset voltage applied between the AIN(+) and AIN(–) pins for
the calibration to adjust out this error is
±
0.05
×
V
REF
(
i.e., the
AIN(+) can be 0.05
×
V
REF
above AIN(–) or 0.05
×
V
REF
below
AIN(–)
). For the system gain error the maximum allowable
system full-scale voltage, in unipolar mode, that can be applied
between AIN(+) and AIN(–) for the calibration to adjust out
this error is V
REF
±
0.025
×
V
REF
(
i.e.
,
the AIN(+) can be V
REF
+
0.025
×
V
REF
above AIN(–) or V
REF
–
0.025
×
V
REF
above
AIN(–)
). If the system offset or system gain errors are outside
the ranges mentioned, the system calibration algorithm will
reduce the errors as much as the trim range allows.
Figures 28 through 30 illustrate why a specific type of system
calibration might be used. Figure 29 shows a system offset cali-
bration (assuming a positive offset) where the analog input
range has been shifted upwards by the system offset after the
system offset calibration is completed. A negative offset may
also be accounted for by a system offset calibration.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7851AN | 14-Bit 333 kSPS Serial A/D Converter |
| AD7851AR | 14-Bit 333 kSPS Serial A/D Converter |
| AD7851ARS | 14-Bit 333 kSPS Serial A/D Converter |
| AD7851KN | 14-Bit 333 kSPS Serial A/D Converter |
| AD7851KR | 14-Bit 333 kSPS Serial A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7851AN | 制造商:Analog Devices 功能描述:ADC Single SAR 333ksps 14-bit Serial 24-Pin PDIP 制造商:Rochester Electronics LLC 功能描述:14 BIT SELF CALIBRATION ADC I.C. - Bulk |
| AD7851ANZ | 功能描述:IC ADC 14BIT SRL 333KSPS 24-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD7851AR | 制造商:Analog Devices 功能描述:ADC Single SAR 333ksps 14-bit Serial 24-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:14 BIT SELF CALIBRATION ADC I.C. - Bulk |
| AD7851AR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 333ksps 14-bit Serial 24-Pin SOIC W T/R |
| AD7851ARS | 制造商:Analog Devices 功能描述:ADC Single SAR 333ksps 14-bit Serial 24-Pin SSOP 制造商:Analog Devices 功能描述:IC 14-BIT ADC |
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