
–31–
REV. A
AD7851
AD7851 to ADSP-21xx Interface
Figure 47 shows the AD7851 interface to the ADSP-21xx. T he
ADSP-21xx is the slave and the AD7851 is the master. T he
AD7851 is in Interface Mode 5. For the ADSP-21xx, the bits in
the serial port control register should be set up as T FSR =
RFSR = 1 (need a frame sync for every transfer), SLEN = 15
(16-bit word length), T FSW = RFSW = 1 (alternate framing
mode for transmit and receive operations), INVRFS = INVT FS
= 1 (active low RFS and T FS), IRFS = IT FS = 0 (External
RFS and T FS), and ISCLK = 0 (external serial clock). T he
CLK IN and
CONVST
signals could be supplied from the
ADSP-21xx or from an external source. T he AD7851 supplies
the SCLK and the
SYNC
signals to the ADSP-21xx and the
reading and writing takes place during conversion. T he BUSY
signal only indicates when the conversion is finished and may
not be required. T he data access and hold times of the ADSP-
21xx and the AD7851 allows for a CLK IN of 7 MHz/6 MHz
with a 5 V supply.
AD7851
CONVST
CLKIN
SCLK
DOUT
BUSY
SM1
SM2
POLARITY
OPTIONAL
7MHz/6MHz
SYNC
RFS
DIN AT DGND FOR
NO WRITING TO PART
SLAVE
MASTER
OPTIONAL
DIN
DV
DD
OPTIONAL
IRQ
DT
TFS
ADSP-21xx
DR
SCK
Figure 47. ADSP-21xx Interface
AD7851 to DSP56000/1/2/L002 Interface
Figure 48 shows the AD7851 to DSP56000/1/2/L002 interface.
Here the DSP5600x is the master and the AD7851 is the slave.
T he AD7851 is in Interface Mode 3. T he setting of the bits in
the registers of the DSP5600x would be for synchronous opera-
tion (SYN = 1), internal frame sync (SCD2 = 1), Internal clock
(SCK D = 1), 16-bit word length (WL1 = 1, WL0 = 0), frames
sync only active at beginning of the transfer (FSL1 = 0, FSL0 =
1). A gated clock can be used (GCK = 1) or if the SCLK is to
be tied to the CLK IN of the AD7851, then there must be a con-
tinuous clock (GCK = 0). Again the data access and hold times
of the DSP5600x and the AD7851 should allow for an SCLK of
7 MHz/6 MHz.
AD7851
CONVST
CLKIN
SCLK
DOUT
BUSY
SM1
SM2
POLARITY
OPTIONAL
7MHz/6MHz
SYNC
DIN AT DGND FOR
NO WRITING TO PART
SLAVE
OPTIONAL
DIN
DV
DD
OPTIONAL
DSP
56000/1/2/L002
SRD
SCK
SC2
MASTER
IRQ
STD
Figure 48. DSP56000/1/2 Interface
AD7851 to T MS320C20/25/5x/LC5x Interface
Figure 49 shows the AD7851 to the T MS320Cxx interface. T he
AD7851 is the master and operates in Interface Mode 5. For
the T MS320Cxx the CLK X , CLK R, FSX , and FSR pins
should all be configured as inputs. T he CLK X and the CLK R
should be connected together as should the FSX and FSR. Since
the AD7851 is the master and the reading and writing occurs
during the conversion, the BUSY only indicates when the con-
version is finished and thus may not be required. Again the data
access and hold times of the T MS320Cxx and the AD7851 al-
lows for a CLK IN of 7 MHz/6 MHz.
AD7851
CONVST
CLKIN
SCLK
DOUT
BUSY
SM1
SM2
POLARITY
OPTIONAL
7MHz/6MHz
SYNC
DIN AT DGND FOR
NO WRITING TO PART
SLAVE
MASTER
OPTIONAL
DIN
DV
DD
OPTIONAL
DT
FSX
INT0
TMS320C20/
25/5x/LC5x
DR
CLKR
FSR
CLKX
Figure 49. TMS320C20/25/5x Interface