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參數(shù)資料
| 型號： | AD7854SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | 0.600 INCH, CERDIP-28 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 264K |
| 代理商： | AD7854SQ |
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AD7854/AD7854L
–
14
–
REV. B
INPUT FREQUENCY
–
kHz
–
72
–
920
100
20
T
–
40
60
80
–
76
–
80
–
84
–
88
R
IN
= 1k
R
= 50 , 10nF
AS IN FIGURE 13
THD
VS.
FREQUENCY
FOR
DIFFERENT
SOURCE
IMPEDANCES
Figure 10. THD vs. Analog Input Frequency
The maximum source impedance depends on the amount of
total harmonic distortion (THD) that can be tolerated. The
THD increases as the source impedance increases. Figure 10
shows a graph of the total harmonic distortion vs. analog input
signal frequency for different source impedances. With the
setup as in Figure 11, the THD is at the
–
90 dB level. With a
source impedance of 1 k
and no capacitor on the AIN(+) pin,
the THD increases with frequency.
In a single supply application (both 3 V and 5 V), the V+ and
V
–
of the op amp can be taken directly from the supplies to the
AD7854/AD7854L which eliminates the need for extra external
power supplies. When operating with rail-to-rail inputs and out-
puts at frequencies greater than 10 kHz, care must be taken in
selecting the particular op amp for the application. In particular,
for single supply applications the input amplifiers should be
connected in a gain of
–
1 arrangement to get the optimum per-
formance. Figure 11 shows the arrangement for a single supply
application with a 50
and 10 nF low-pass filter (cutoff fre-
quency 320 kHz) on the AIN(+) pin. Note that the 10nF is a
capacitor with good linearity to ensure good ac performance.
Recommended single supply op amps are the AD820 and the
AD820-3V.
V
–
V+
10k
10k
V
(
–
V
REF
/2 TO +V
REF
/2)
V
REF
/2
0.1 F
10 F
50
10nF
(NPO)
AD820
AD820-3V
TO AIN(+) OF
AD7854/AD7854L
+3V TO +5V
10k
IC1
10k
Figure 11. Analog Input Buffering
ANALOG INPUT
The equivalent analog input circuit is shown in Figure 9. Dur-
ing the acquisition interval the switches are both in the track
position and the AIN(+) charges the 20 pF capacitor through
the 125
resistance. On the rising edge of
CONVST
switches
SW1 and SW2 go into the hold position retaining charge on the
20 pF capacitor as a sample of the signal on AIN(+). The
AIN(
–
) is connected to the 20 pF capacitor, and this unbalances
the voltage at Node A at the input of the comparator. The
capacitor DAC adjusts during the remainder of the conversion
cycle to restore the voltage at Node A to the correct value. This
action transfers a charge, representing the analog input signal, to
the capacitor DAC which in turn forms a digital representation
of the analog input signal. The voltage on the AIN(
–
) pin directly
influences the charge transferred to the capacitor DAC at the
hold instant. If this voltage changes during the conversion period,
the DAC representation of the analog input voltage is altered.
Therefore it is most important that the voltage on the AIN(
–
)
pin remains constant during the conversion period. Further-
more, it is recommended that the AIN(
–
) pin is always connected
to AGND or to a fixed dc voltage.
CAPACITOR
DAC
COMPARATOR
20pF
HOLD
TRACK
SW2
TRACK
SW1
HOLD
125
AIN(+)
125
AIN(
–
)
AGND
NODE A
Figure 9. Analog Input Equivalent Circuit
Acquisition Time
The track-and-hold amplifier enters its tracking mode on the
falling edge of the BUSY signal. The time required for the
track-and-hold amplifier to acquire an input signal depends on
how quickly the 20 pF input capacitance is charged. There is a
minimum acquisition time of 400 ns. For large source imped-
ances, >2 k
, the acquisition time is calculated using the formula:
t
ACQ
= 9
×
(R
IN
+ 125
)
×
20
pF
where
R
IN
is the source impedance of the input signal, and
125
, 20
pF
is the input R, C.
DC/AC Applications
For dc applications, high source impedances are acceptable,
provided there is enough acquisition time between conversions
to charge the 20 pF capacitor. For example with R
IN
= 5 k
,
the required acquisition time is 922 ns.
For ac applications, removing high frequency components from
the analog input signal is recommended by use of an RC low-
pass filter on the AIN(+) pin, as shown in Figure 11. In applica-
tions where harmonic distortion and signal to noise ratio are
critical, the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac per-
formance of the ADC. They may require the use of an input
buffer amplifier. The choice of the amplifier is a function of the
particular application.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7854L* | 3.3V/5V Low Power RS232 3-Driver/5-Receiver Transceiver; Package: SSOP; No of Pins: 28; Temperature Range: 0°C to +70°C |
| AD7854BR | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7854AR | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7854L | 12-Bit Sampling ADC(單電源,200kSPS 12位采樣A/D轉(zhuǎn)換器) |
| AD7854 | 12-Bit Sampling ADC(單電源,200kSPS 12位采樣A/D轉(zhuǎn)換器) |
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