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參數資料
| 型號： | AD7854SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | 0.600 INCH, CERDIP-28 |
| 文件頁數： | 9/28頁 |
| 文件大小： | 264K |
| 代理商： | AD7854SQ |
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AD7854/AD7854L
REV. B
–
9
–
CONTROL REGISTER
The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The
control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register is described
below. The power-up status of all bits is 0.
MSB
ZERO
ZERO
ZERO
ZERO
PMGT1
PMGT0
RDSLT1
RDSLT0
AMODE
CONVST
CALMD
CALSLT1
CALSLT0
STCAL
LSB
Control Register Bit Function Description
Bit
Mnemonic
Comment
13
12
11
10
9
8
7
6
5
ZERO
ZERO
ZERO
ZERO
PMGT1
PMGT0
RDSLT1
RDSLT0
AMODE
These four bits must be set to 0 when writing to the control register.
Power Management Bits. These two bits are used for putting the part into various power-down modes
(See
Power-Down
section for more details).
Theses two bits determine which register is addressed for the read operations. See Table II.
Analog Mode Bit. This pin allows two different analog input ranges to be selected. A logic 0 in this bit
position selects range 0 to V
REF
(i.e., AIN(+)
–
AIN(
–
) = 0 to V
REF
). In this range AIN(+) cannot go
below AIN(
–
) and AIN(
–
) cannot go below AGND and data coding is straight binary. A logic 1 in this
bit position selects range
–
V
REF
/2 to +V
REF
/2 (i.e., AIN(+)
–
AIN(
–
) =
–
V
REF
/2 to +V
REF
/2). AIN(+)
cannot go below AGND, so for this range, AIN(
–
) needs to be biased to at least +V
REF
/2 to allow
AIN(+) to go as low as AIN(
–
)
–
V
REF
/2 V. Data coding is twos complement for this range.
Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati-
cally reset to 0 at the end of conversion. This bit may also used in conjunction with system calibration
(see Calibration section).
Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III).
Calibration Selection Bits and Start Calibration Bit. These bits have two functions.
With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per-
formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration.
With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration
register for read/write of calibration coefficients (see section on the calibration registers for more details).
4
CONVST
3
2
1
0
CALMD
CALSLT1
CALSLT0
STCAL
Table III. Calibration Selection
CALMD
CALSLT1
CALSLT0
Calibration Type
0
0
0
A
full internal calibration
is initiated. First the internal DAC is calibrated, then the
internal gain error and finally the internal offset error are removed. This is the default setting.
First the
internal gain error
is removed, then the
internal offset error
is removed.
The
internal offset error
only is calibrated out.
The
internal gain error
only is calibrated out.
A
full system calibration
is initiated. First the internal DAC is calibrated, followed by the
system gain error calibration, and finally the system offset error calibration.
First the
system gain error
is calibrated out followed by the
system offset error
.
The
system offset error
only is removed.
The
system gain error
only is removed.
0
0
0
1
0
1
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
相關PDF資料 |
PDF描述 |
|---|---|
| AD7854L* | 3.3V/5V Low Power RS232 3-Driver/5-Receiver Transceiver; Package: SSOP; No of Pins: 28; Temperature Range: 0°C to +70°C |
| AD7854BR | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7854AR | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| AD7854L | 12-Bit Sampling ADC(單電源,200kSPS 12位采樣A/D轉換器) |
| AD7854 | 12-Bit Sampling ADC(單電源,200kSPS 12位采樣A/D轉換器) |
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