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參數資料
| 型號： | AD8370-EVAL |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | LF to 750 MHz Digitally Controlled VGA |
| 中文描述： | LF到750兆赫數字控制VGA |
| 文件頁數： | 14/28頁 |
| 文件大小： | 1043K |
| 代理商： | AD8370-EVAL |
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AD8370
OUTPUT AMPLIFIER
The output impedance is approximately 100 differential and,
like the input preamplifier, this impedance is formed using
active circuit elements. See Figure 38 for a simplified schematic
of the output interface.
Rev. 0 | Page 14 of 28
Table 4. Serial Programming Timing Parameters
Parameter
Clock Pulse Width (T
PW
)
Clock Period (T
CK
)
Setup Time Data vs. Clock (T
DS
)
Setup Time Latch vs. Clock (T
ES
)
Hold Time Latch vs. Clock (T
EH
)
Min
25
50
10
20
10
Unit
ns
ns
ns
ns
ns
VCC/2
740
OPHI/OPLO
0
10
μ
A
CLCK/DATA/LTCH/PWUP
0
Figure 38. OPHI/OPLO Simplified Circuit
Figure 40. Simplified Circuit for Digital Inputs
The gain of the output amplifier, and thus the AD8370 as a
whole, is load dependent. The following equation can be used to
predict the gain deviation of the AD8370 from that at 100 as
the load is varied:
VCC/2
75
VOCM
0
LOAD
R
ion
GainDeviat
98
1
98
.
+
=
For example, if
R
LOAD
is 1 k, the gain is a factor of 1.80 (5.12 dB)
above
that at 100 , all other things being equal. If
R
LOAD
is 50 ,
the gain is a factor of 0.669 (3.49 dB)
below
that at 100 .
Figure 41. Simplified Circuit for VOCM Output
DIGITAL INTERFACE AND TIMING
The digital control port uses a standard TTL interface. The 8-bit
control word is read in a serial fashion when the LTCH pin is
held low. The levels presented to the DATA pin are read on each
rising edge of the CLCK signal. Figure 39 illustrates the timing
diagram for the control interface. Minimum values for timing
parameters are presented in Table 4. Figure 40 is a simplified
schematic of the digital input pins.
DATA
(Pin 14)
CLCK
(Pin 13)
LTCH
(Pin 12)
T
DS
T
ES
T
EH
MSB
MSB-1 MSB-2 MSB-3
LSB
LSB+1
LSB+2
LSB+3
T
CK
T
PW
0
Figure 39. Digital Timing Diagram
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