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參數資料
| 型號： | AD8370-EVAL |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | LF to 750 MHz Digitally Controlled VGA |
| 中文描述： | LF到750兆赫數字控制VGA |
| 文件頁數： | 6/28頁 |
| 文件大小： | 1043K |
| 代理商： | AD8370-EVAL |
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AD8370
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
Rev. 0 | Page 6 of 28
6
7
8
11
10
9
AD8370
TOP VIEW
(Not to Scale)
2
3
4
5
15
14
1
16
13
12
0
INHI
ICOM
VCCI
PWUP
VOCM
VCCO
OCOM
OPHI
OPLO
OCOM
VCCO
LTCH
CLCK
DATA
ICOM
INLO
Figure 3.16-Lead TSSOP
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
1
INHI
2, 15,
PADDLE
3
VCCI
4
PWUP
5
VOCM
Description
Balanced Differential Input. Internally biased.
Input Common. Connect to a low impedance ground. This node is also connected to the exposed pad on the
bottom of the device.
Input Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed.
Power Enable Pin. Device is operational when PWUP is pulled high.
Common-Mode Output Voltage Pin. The midsupply ((V
VCCO
V
OCOM
)/2) common-mode voltage is delivered to
this pin for external bypassing for additional common-mode supply decoupling. This can be achieved with a
bypass capacitor to ground. This pin is an output only and is not to be driven externally.
Output Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed.
Output Common. Connect to a low impedance ground.
Balanced Differential Output. Biased to midsupply.
Balanced Differential Output. Biased to midsupply.
Serial Data Latch Pin. Serial data is clocked into the shift register via the DATA pin when LTCH is low. Data in
shift register is latched on the next high-going edge.
Serial Clock Input Pin.
Serial Data Input Pin.
Balanced Differential Input. Internally biased.
ICOM
6, 11
7, 10
8
9
12
VCCO
OCOM
OPHI
OPLO
LTCH
13
14
16
CLCK
DATA
INLO
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