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參數資料
| 型號： | AD8370-EVAL |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運動控制電子 |
| 英文描述： | LF to 750 MHz Digitally Controlled VGA |
| 中文描述： | LF到750兆赫數字控制VGA |
| 文件頁數： | 17/28頁 |
| 文件大小： | 1043K |
| 代理商： | AD8370-EVAL |
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AD8370
Due to the nature of the AD8370’s circuit design, care must be
taken to minimize parasitic capacitance on the input and output.
The AD8370 could become unstable with more than a few pF of
shunt capacitance on each input. Using resistors in series with
input pins is recommended under conditions of high source
capacitance.
Rev. 0 | Page 17 of 28
High transient and noise levels on the power supply, ground,
and digital inputs can, under some circumstances, reprogram the
AD8370 to an unintended gain code. This further reinforces the
need for proper supply bypassing and decoupling. The user
should also be aware that probing the AD8370 and associated
circuitry during circuit debug may also induce the same effect.
PACKAGE CONSIDERATIONS
The package of the AD8370 is a compact, thermally enhanced
TSSOP 16-lead design. A large exposed paddle on the bottom of
the device provides both a thermal benefit and a low inductance
path to ground for the circuit. To make proper use of this pack-
aging feature, the PCB needs to make contact directly under the
device, connected to an ac/dc common ground reference with
as many vias as possible to lower the inductance and thermal
impedance.
SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION
AD8370
I
I
V
P
V
V
O
O
O
O
V
L
C
D
I
I
6
7
8
2
3
5
1
11
10
9
15
14
16
13
12
4
SERIAL CONTROL
INTERFACE
0.1
μ
F
1nF
0.1
μ
F
+V
S
C
AC
C
AC
C
AC
C
AC
R
L
SINGLE-
ENDED
SOURCE
R
S
0
Figure 45. Single-Ended-to-Differential Conversion
The AD8370 is primarily designed for differential signal inter-
facing. The device can be used for single-ended-to-differential
conversion simply by terminating the unused input to ground
using a capacitor as depicted in Figure 45. The ac coupling
capacitors should be selected such that their reactance is negli-
gible at the frequency of operation. For example, using 1 nF
capacitors for C
AC
presents a capacitive reactance of –j1.6 on
each input node at 100 MHz. This attenuates the applied input
voltage by 0.003 dB. If 10 pF capacitors had been selected, the
voltage delivered to the input would be reduced by 2.1 dB when
operating with a 200 source impedance.
D
–1.0
0
–0.5
0.5
0
100
200
300
400
500
FREQUENCY (MHz)
0
HIGH GAIN MODE
(GAIN CODE HG255)
LOW GAIN MODE
(GAIN CODE LG127)
Figure 46. Differential Output Balance for a Single-Ended Input Drive at
Maximum Gain (R
L
= 1 k, C
AC
= 10 nF)
Figure 46 illustrates the differential balance at the output for a
single-ended input drive for multiple gain codes. The differential
balance is better than 0.5 dB for signal frequencies less than
250 MHz. Figure 47 depicts the differential balance over the
entire gain range at 10 MHz. The balance is degraded for lower
gain settings because the finite common gain allows some of the
input signal applied to INHI to pass directly through to the
OPLO pin. At higher gain settings, the differential gain dominates
and balance is restored.
0
0.1
0.2
0.3
0.4
0.5
0.6
D
0
96
32
64
0
32
64
96
128
GAIN CODE
0
LOW GAIN MODE
HIGH GAIN MODE
Figure 47. Differential Output Balance at 10 MHz for a Single-Ended Drive vs.
Gain Code (R
L
= 1 k, C
AC
= 10 nF)
Even though the amplifier is no longer being driven in a bal-
anced manner, the distortion performance remains adequate for
most applications. Figure 48 illustrates the harmonic distortion
performance of the circuit in Figure 45 over the entire gain range.
If the amplifier is driven in single-ended mode, the input
impedance varies depending on the value of the resistor used to
terminate the other input as follows:
Rin
SE
=
Rin
DIFF
+
R
TERM
where
R
TERM
is the termination resistor connected to the other
input.
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