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參數資料
| 型號： | AD9446-80LVDS |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 80/100 MSPS ADC |
| 中文描述： | 16位，80/100 MSPS的模數轉換器 |
| 文件頁數： | 25/36頁 |
| 文件大小： | 952K |
| 代理商： | AD9446-80LVDS |
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AD9446
Table 9. Reference Configuration Summary
Selected Mode
External Reference
Programmable Reference
Rev. 0 | Page 25 of 36
SENSE Voltage
AVDD
0.2 V to VREF
Resulting VREF (V)
N/A
+
×
1
0.5
Resulting Differential Span (V p-p)
2 × external reference
2 × VREF
R1
R2
R2
(See Figure 56)
Programmable Reference
(Set for 2 V p-p)
0.2 V to VREF
+
×
R1
R2
1
0.5
, R1 = R2 = 1 kΩ
2.0
Programmable Reference
(Set for 2 V p-p)
0.2 V to VREF
+
×
R1
1
0.5
, R1 = 1 kΩ , R2 = 2.8 kΩ
3.8
Internal Fixed Reference
AGND to 0.2 V
1.6
3.2
External Reference Operation
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 2.0 V See Figure 46 for gain variation vs.
temperature.
Analog Inputs
As with most new high speed, high dynamic range ADCs, the
analog input to the AD9446 is differential. Differential inputs
improve on-chip performance because signals are processed
through attenuation and gain stages. Most of the improvement
is a result of differential analog stages having high rejection of
even-order harmonics. There are also benefits at the PCB level.
First, differential inputs have high common-mode rejection of
stray signals, such as ground and power noise. Second, they
provide good rejection of common-mode signals, such as local
oscillator feedthrough. The specified noise and distortion of the
AD9446 cannot be realized with a single-ended analog input, so
such configurations are discouraged. Contact sales for
recommendations of other 16-bit ADCs that support single-
ended analog input configurations.
With the 1.6 V reference, which is the nominal value (see the
Internal Reference Trim section), the differential input range of
the AD9446 analog input is nominally 3.2 V p-p or 1.6 V p-p on
each input (VIN+ or VIN).
3.5V
VIN+
VIN–
1.6V p-p
DIGITAL OUT = ALL 1s
DIGITAL OUT = ALL 0s
0
Figure 57. Differential Analog Input Range for VREF = 1.6 V
The AD9446 analog input voltage range is offset from ground
by 3.5 V. Each analog input connects through a 1 kΩ resistor to
the 3.5 V bias voltage and to the input of a differential buffer. The
internal bias network on the input properly biases the buffer for
maximum linearity and range (see the Equivalent Circuits
section). Therefore, the analog source driving the AD9446
should be ac-coupled to the input pins. The recommended
method for driving the analog input of the AD9446 is to use an
RF transformer to convert single-ended signals to differential
(see Figure 58). Series resistors between the output of the
transformer and the AD9446 analog inputs help isolate the
analog input source from switching transients caused by the
internal sample-and-hold circuit. The series resistors, along
with the 1 kΩ resisters connected to the internal 3.5 V bias,
must be considered in impedance matching the transformer
input. For example, if R
T
is set to 51 Ω, R
S
is set to 33 Ω and
there is a 1:1 impedance ratio transformer, the input will match a
50 Ω source with a full-scale drive of 16.0 dBm. The 50 Ω
impedance matching can also be incorporated on the secondary
side of the transformer, as shown in the evaluation board
schematic (see Figure 61).
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