- 您現在的位置：買賣IC網 > PDF目錄373963 > AD9446-80LVDS (Analog Devices, Inc.) 16-Bit, 80/100 MSPS ADC PDF資料下載
參數資料
| 型號： | AD9446-80LVDS |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 80/100 MSPS ADC |
| 中文描述： | 16位，80/100 MSPS的模數轉換器 |
| 文件頁數： | 27/36頁 |
| 文件大小： | 952K |
| 代理商： | AD9446-80LVDS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
AD9446
POWER CONSIDERATIONS
Care should be taken when selecting a power source. The use of
linear dc supplies is highly recommended. Switching supplies
tend to have radiated components that may be received by the
AD9446. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 μF chip capacitors.
Rev. 0 | Page 27 of 36
The AD9446 has separate digital and analog power supply pins.
The analog supplies are denoted AVDD1 (3.3 V) and AVDD2
(5 V), and the digital supply pins are denoted DRVDD. Although
the AVDD1 and DRVDD supplies can be tied together, best per-
formance is achieved when the supplies are separate. This is
because the fast digital output swings can couple switching
current back into the analog supplies. Note that both AVDD1
and AVDD2 must be held within 5% of the specified voltage.
The DRVDD supply of the AD9446 is a dedicated supply for the
digital outputs in either LVDS or CMOS output mode. When in
LVDS mode, the DRVDD should be set to 3.3 V In CMOS mode,
the DRVDD supply can be connected from 2.5 V to 3.6 V for
compatibility with the receiving logic.
DIGITAL OUTPUTS
LVDS Mode
The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin 3 (OUTPUT MODE).
LVDS outputs are available when OUTPUT MODE is CMOS
logic high (or AVDD1 for convenience) and a 3.74 kΩ R
SET
resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic
performance, including both SFDR and SNR, is maximized
when the AD9446 is used in LVDS mode; designers are
encouraged to take advantage of this mode. The AD9446
outputs include complimentary LVDS outputs for each data bit
(Dx+/Dx), the overrange output (OR+/OR), and the output
data clock output (DCO+/DCO). The R
SET
resistor current is
multiplied on-chip, setting the output current at each output
equal to a nominal 3.5 mA (11 × I
RSET
). A 100 Ω differential
termination resistor placed at the LVDS receiver inputs results
in a nominal 350 mV swing at the receiver. LVDS mode
facilitates interfacing with LVDS receivers in custom ASICs and
FPGAs that have LVDS capability for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended, with a 100 Ω termination resistor
located as close to the receiver as possible. It is recommended to
keep the trace length less than 2 inches and to keep differential
output trace lengths as equal as possible.
CMOS Mode
In applications that can tolerate a slight degradation in dynamic
performance, the AD9446 output drivers can be configured to
interface with 2.5 V or 3.3 V logic families by matching
DRVDD to the digital supply of the interfaced logic. CMOS
outputs are available when OUTPUT MODE is CMOS logic
low (or AGND for convenience). In this mode, the output data
bits, Dx, are single-ended CMOS, as is the overrange output,
OR+. The output clock is provided as a differential CMOS
signal, DCO+/DCO. Lower supply voltages are recommended
to avoid coupling switching transients back to the sensitive
analog sections of the ADC. The capacitive load to the CMOS
outputs should be minimized, and each output should be
connected to a single gate through a series resistor (220 Ω) to
minimize switching transients caused by the capacitive loading.
TIMING
The AD9446 provides latched data outputs with a pipeline delay
of 13 clock cycles. Data outputs are available one propagation
delay (t
PD
) after the rising edge of CLK+. Refer to Figure 2 and
Figure 3 for detailed timing diagrams.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9446-80PCB | 16-Bit, 80/100 MSPS ADC |
| AD9480 | 8-Bit, 250 MSPS 3.3 V A/D Converter |
| AD9480-LVDS-PCB3 | 8-Bit, 250 MSPS 3.3 V A/D Converter |
| AD9480ASUZ-2501 | 8-Bit, 250 MSPS 3.3 V A/D Converter |
| AD9480BSUZ-2501 | 8-Bit, 250 MSPS 3.3 V A/D Converter |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9446-80LVDS/PCB | 制造商:Analog Devices 功能描述:EVAL KIT FOR 16BIT, 80/100 MSPS ADC - Bulk |
| AD9446-80LVDS/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9446-80 制造商:Analog Devices 功能描述:16-BIT 180MSPS ADC EVAL BD - Bulk |
| AD9446-80LVDSPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Speed ADC USB FIFO Evaluation Kit |
| AD9446-80PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 80/100 MSPS ADC |
| AD9446BSVZ-100 | 功能描述:模數轉換器 - ADC 16Bit 100 MSPS ADC RoHS:否 制造商:Analog Devices 通道數量: 結構: 轉換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
發布緊急采購，3分鐘左右您將得到回復。