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參數(shù)資料
| 型號： | AD9847 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver |
| 中文描述： | 10位40 MSPS的CCD信號處理器集成時序驅(qū)動 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大小： | 428K |
| 代理商： | AD9847 |
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REV. A
AD9847
–10–
Bit
Content
Default
Value
Address
Width
Register Name
Register Description
AFE Registers # Bits 56
00
01
02
03
04
05
06
07
08
09
0A
[5:0]
[1:0]
[5:0]
[3:0]
[5:0]
[1:0]
[5:0]
[5:0]
[5:0]
[5:0]
[5:0]
6
2
6
4
6
2
6
6
6
6
6
00
00
16
02
00
02
00
00
00
00
00
oprmode[5:0]
oprmode[7:6]
ccdgain[5:0]
ccdgain[9:6]
refblack[5:0]
refblack[7:6]
ctlmode
pxga gain0
pxga gain1
pxga gain2
pxga gain3
AFE Operation Mode (See AFE Register Breakdown)
VGA Gain
Black Clamp Level
Control Mode (See AFE Register Breakdown)
PxGA
Color 0 Gain
PxGA
Color 1 Gain
PxGA
Color 2 Gain
PxGA
Color 3 Gain
Miscellaneous/Extra # Bits 26
0F
[5:0]
6
00
INITIAL2
See Recommended Power Up Sequence Section. Should be
set to “4” decimal (000100).
Output Control (0 = Make All Outputs DC Inactive)
Serial Data Update Control (Sets the line within the field
for serial data update to occur)
Prevent the Update of the VD/HD Updated Registers
DOUT Phase Control
Disable CCDIN DC Restore Circuit During PBLK
(1 = Disable)
VD/HD Active Polarity (0 = Low Active, 1 = High Active)
Internal Field Pulse Value (0 = Next Field Odd,
1 = Next Field Even)
Re-Sync hblk to h1 Clock
See Recommended Power Up Sequence. Should be set to
“53” decimal (110101).
TG Core Reset_Bar (0 = Hold TG Core in Reset,
1 = Resume Normal Operation)
16
17
18
19
1B
1C
[0]
[5:0]
[5:0]
[0]
[5:0]
[0]
1
6
6
1
6
1
00
00
00
00
00
00
out_cont
update[5:0]
update[11:6]
preventupdate
doutphase
disablerestore
1D
1E
[0]
[0]
1
1
00
01
vdhdpol
fieldval
1F
20
[0]
[5:0]
1
6
00
00
hblkretime
INITIAL1
26
[0]
1
00
tgcore_rstb
Accessing a Double-Wide Register
There are many double-wide registers in the AD9847, e.g.,
oprmode, clpdmtog1_0, and clpdmscp3, and so on. These regis-
ters are configured into two consecutive 6-bit registers with the
least significant six bits located in the lower of the two addresses
and the remaining most significant bits located in the higher of
the two addresses. For example, the six LSBs of the clpdmscp3
register, clpdmscp3[5:0], are located at address 0x81. The most
significant six bits of the clpdmscp3 register, clpdmscp3[11:6],
are located at Address 0x82. The following rules must be fol-
lowed when accessing double-wide registers:
1. When accessing a double-wide register, BOTH addresses
must be written to.
2. The lower of the two consecutive addresses for the double-
wide register must be written to first. In the example of the
clpdmscp3 register, the contents of Address 0x81 must be
written first, followed by the contents of Address 0x82. The
register will be updated after the completion of the write to
Register 0x82, either at the next SL rising edge or the next
VD/HD falling edge.
3. A single write to the lower of the two consecutive addresses
of a double-wide register that is not followed by a write to the
higher address of the registers is not permitted. This will not
update the register.
4. A single write to the higher of the two consecutive addresses of a
double-wide register that is not preceded by a write to the lower
of the two addresses is not permitted. Although the write to the
higher address will update the full double-wide register, the
lower six bits of the register will be written with an indetermi-
nate value if the lower address was not written to first.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9847AKST | 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver |
| AD9848KST | CCD Signal Processors with Integrated Timing Driver |
| AD9848 | CCD Signal Processors with Integrated Timing Driver |
| AD9849 | CCD Signal Processors with Integrated Timing Driver |
| AD9849KST | CCD Signal Processors with Integrated Timing Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9847AKCPZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9847AKCPZRL | 制造商:Analog Devices 功能描述:DISPLAY DRVR, 10-BIT 40MSPS CCD SGNL PROCESSOR W/ INTEGRATED - Tape and Reel |
| AD9847AKST | 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V/5V/5V 48L - Trays |
| AD9847AKSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3.3V/5V 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V/5V/5V 48L - Tape and Reel |
| AD9847AKSTZ | 功能描述:IC CCD SIGNAL PROC 10BIT 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
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