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參數(shù)資料
| 型號(hào)： | AD9847 |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver |
| 中文描述： | 10位40 MSPS的CCD信號(hào)處理器集成時(shí)序驅(qū)動(dòng) |
| 文件頁(yè)數(shù)： | 9/28頁(yè) |
| 文件大?。?/td> | 428K |
| 代理商： | AD9847 |
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REV. A
AD9847
–9–
SERIAL INTERFACE TIMING
SDATA
A0
A1
A2
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
XX
XX
SCK
SL
A3
NOTES
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES.
2. 14 SCK EDGES ARE NEEDED TO WRITE ADDRESS AND DATA BITS.
3. FOR 16-BIT SYSTEMS, TWO EXTRA DUMMY BITS MAY BE WRITTEN. DUMMY BITS ARE IGNORED.
4. NEW DATA IS UPDATED EITHER AT THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
VD
HD
SL UPDATED
VD/HD UPDATED
t
DS
t
DH
t
LS
t
LH
Figure 3a. Serial Write Operation
SDATA
A0
A1
A2
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
SCK
SL
A3
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 6-BIT DATA-WORDS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 6-BIT DATA-WORD (ALL SIX BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED EITHER AT THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
D0
D1
D2
D3
D4
D5
D0
...
...
...
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
D2
D1
Figure 3b. Continuous Serial Write Operation
COMPLETE REGISTER LISTING
Table I. SL Updated Registers
Register
oprmode
ctlmode
preventpdate
readback
vdhdpol
fieldval
hblkretime
tgcore_rstb
h12pol
h1posloc
h1negloc
Description
AFE Operation Modes
AFE Control Modes
Prevents Loading of VD-Updated Registers
Enables Serial Register Readback Mode
VD/HD Active Polarity
Internal Field Pulse Value
Retimes the H1 hblk to Internal Clock
Reset Bar Signal for Internal TG Core
H1/H2 Polarity Control
H1 Positive Edge Location
H1 Negative Edge Location
Register
h1drv
h2drv
h3drv
h4drv
rgpol
rgposloc
rgnegloc
rgdrv
shpposloc
shdposloc
Description
H1 Drive Current
H2 Drive Current
H3 Drive Current
H4 Drive Current
RG Polarity
RG Positive Edge Location
RG Negative Edge Location
RG Drive Current
SHP Sample Location
SHD Sample Location
NOTES
All addresses and default values are expressed in hexadecimal.
All registers are VD/HD updated as shown in Figure 3a, except for those that are SL updated.
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