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參數(shù)資料
| 型號： | AD9847 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver |
| 中文描述： | 10位40 MSPS的CCD信號處理器集成時序驅動 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 428K |
| 代理商： | AD9847 |
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REV. A
AD9847
–15–
Bit
Content
Default
Value
Address
Width
Register Name
Register Description
AFE Register Breakdown
Serial Address:
8'h00 {oprmode[5:0]}, 8'h01 {oprmode[7:6]}
oprmode
[7:0]
8'h0
[1:0]
2'h0
2'h1
2'h2
2'h3
powerdown[1:0]
Full Power
Fast Recovery
Reference Standby
Total Shutdown
Disable Black Loop Clamping (High Active)
Test Mode—Should Be Set Low
Test Mode—Should Be Set High
Test Mode—Should Be Set Low
Test Mode—Should Be Set Low
Test Mode—Should Be Set Low
[2]
[3]
[4]
[5]
[6]
[7]
disblack
test mode
test mode
test mode
test mode
test mode
ctlmode
[5:0]
6'h0
Serial Address: 8'h06 {cltmode[5:0]}
[2:0]
3'h0
3'h1
3'h2
3'h3
3'h4
3'h5
3'h6
3'h7
ctlmode[2:0]
Off
Mosaic Separate
VD Selected/Mosaic Interlaced
Mosaic Repeat
Three-Color
Three-Color II
Four-Color
Four-Color II
Enable
PxGA
(High Active)
Latch Output Data on Selected DOUT Edge
Leave Output Latch Transparent
ADC Outputs Are Driven
ADC Outputs Are Three-Stated
[3]
[4]
enablepxga
outputlat
1'h0
1'h1
1'h0
1'h1
[5]
tristateout
PRECISION TIMING HIGH SPEED TIMING
GENERATION
The AD9847 generates flexible high speed timing signals using
the
Precision Timing
core. This core is the foundation for generating
the timing used for both the CCD and the AFE, the reset gate RG,
horizontal drivers H1–H4, and the SHP/SHD sample clocks.
A unique architecture makes it routine for the system designer to
optimize image quality by providing precise control over the hori-
zontal CCD readout and the AFE correlated double sampling.
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
t
CLIDLY
= 6 ns TYP).
P[0]
P[48]=P[0]
P[12]
P[24]
P[36]
1 PIXEL
PERIOD
...
...
CLI
t
CLIDLY
POSITION
Figure 4. High Speed Clock Resolution from CLI Master Clock Input
Timing Resolution
The
Precision Timing
core uses a 1 master clock input (CLI) as
a reference. This clock should be the same as the CCD pixel clock
frequency. Figure 4 illustrates how the internal timing core
divides the master clock period into 48 steps or edge positions.
Therefore, the edge resolution of the
Precision Timing
core is
(t
CLI
/48). For more information on using the CLI input, see the
Applications Information section.
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| AD9847AKST | 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9847AKCPZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9847AKCPZRL | 制造商:Analog Devices 功能描述:DISPLAY DRVR, 10-BIT 40MSPS CCD SGNL PROCESSOR W/ INTEGRATED - Tape and Reel |
| AD9847AKST | 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V/5V/5V 48L - Trays |
| AD9847AKSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3.3V/5V 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:AFE VID 1ADC 10-BIT 3V/3V/3.3V/3.3V/3.3V/3.3V/3.3V/5V/5V 48L - Tape and Reel |
| AD9847AKSTZ | 功能描述:IC CCD SIGNAL PROC 10BIT 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
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