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參數資料
| 型號： | AD9860 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| 中文描述： | 混合寬帶通信信號前端（MxFE⑩）處理器 |
| 文件頁數： | 31/32頁 |
| 文件大小： | 617K |
| 代理商： | AD9860 |
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REV. 0
AD9860/AD9862
–31–
Conversion is initiated by writing a logic high to one or both of
the Start register bits, Register D34 B0 (StartA) and D34 B3
(StartB). When the conversion is complete, the straight binary,
10-bit output data of the AUX ADC is written to one of four
reserved locations in the register map depending on which auxil-
iary ADC and which multiplexed input is selected. Because the
auxiliary ADCs output 10 bits, two register addresses are needed
for each data location.
Initiating a conversion or retrieving data can also be accomplished
either through the standard Serial Port Interface by reading and
writing to the appropriate registers or through a dedicated
Auxiliary Serial Port Interface (AUX SPI). The AUX SPI can
be configured to allow fast access and control of either one of the
auxiliary ADCs and is available so that the SPI is not tied up
retrieving auxiliary ADC data.
The AUX SPI can be enabled and configured by setting register
AUX ADC CTRL. Setting register use pins high enables the
AUX SPI port. Setting register Sel BnotA low connects auxiliary
ADC A to the AUX SPI port, while setting it high connects
auxiliary ADC B to the AUX SPI port. As mentioned above,
setting the appropriate Select bit selects which of the multiplexed
input is connected to the auxiliary ADC.
The AUX SPI consists of a chip select pin (AUX_SPI_csb),
a clock pin (AUX_SPI_clk), and a data output pin (AUX_SPI_do).
A conversion is initiated by pulsing the AUX_SPI_csb pin low.
When the conversion is complete, the data pin, AUX_SPI_do,
previously a logic low, will go high. At this point, the user supplies
an external clock, previously tied low, no data is present on the
first rising edge. The data output bit is updated on the falling
edge of the clock pulse and is settled and can be latched on the
next clock rising edge. The data arrives serially, MSB first. The
AUX SPI runs up to a rate of 16 MHz.
AUX DAC
The AD9860/AD9862 has three 8-bit voltage output auxiliary
DACs, AUX DACs. The AUX DACs are available for supplying
various control voltages throughout the system such as a VCXO
voltage control or external VGA gain control and can typically
sink or source up to 1 mA.
An internal voltage reference buffer provides a full-scale voltage
reference for both of the AUX DACs equal to the supply voltage
for the AUX DACs. The straight binary input codes are written
to the appropriate registers. If the Slave Mode register bit is
high, slave mode enabled, the AUX DAC(s) update will occur
when the appropriate update register is written to. Otherwise,
the update will occur at the conclusion of the data being written
to the register. Typical maximum settling time for the auxiliary
DAC is around 6
m
s.
Other optional controls include an invert register control and a
power down option. The invert register control, i.e., instead of
hexFF being high and hex00 being low, hex00 is high, and hexFF
will be minimum setting.
Sigma-Delta
A 12-bit sigma-delta (SD) output is available to provide an
additional control voltage. The SD control word is written to
Registers D42, 43; SD [11:4] are the 8 MSBs and SD [3:0] are
the 4 LSBs. The 12-bit word is processed by a sigma-delta
modulator and produces 1-bit data at an oversampled rate equal
to 1/8 of the receive ADC
’
s sampling rate (up to 8 MSPS). The
1-bit data then feeds a 1-bit DAC. The 1-bit DAC exhibits
perfect linearity. An external low-pass filter at the output should
be used to low-pass filter the pulse modulated data to produce a
linear output control voltage.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9860BST | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9860PCB | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9862 | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9862BST | Mixed-Signal Front-End (MxFE⑩) Processor for Broadband Communications |
| AD9864 | IF Digitizing Subsystem |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9860BST | 制造商:Analog Devices 功能描述:Mixed Signal Front End 128-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10B MIXED SIGNAL FRONT END MXFE PROCESSO - Tape and Reel |
| AD9860BSTRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 128-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:10B MIXED SIGNAL FRONT END MXFE PROCESSO - Tape and Reel |
| AD9860BSTZ | 功能描述:IC PROCESSOR FRONT END 128LQFP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9860BSTZRL | 功能描述:IC PROCESSOR FRONT END 128LQFP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應商設備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9860-EB | 制造商:Analog Devices 功能描述: |
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