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| 型號(hào)： | AD9866-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | 寬帶調(diào)制解調(diào)器混合信號(hào)前端 |
| 文件頁(yè)數(shù)： | 33/48頁(yè) |
| 文件大小： | 1647K |
| 代理商： | AD9866-EB |
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AD9866
RECEIVE PATH
The receive path block diagram for the AD9866 (or AD9865) is
shown in Figure 68. The receive signal path consists of a 3-stage
RxPGA, a 3-pole programmable LPF, and a 12-bit (or 10-bit)
ADC. Note that the additional 2 bits of resolution offered by the
AD9866 (vs. the AD9865) result in a 3 dB to 5 dB lower noise
floor depending on the RxPGA gain setting and LPF cutoff
frequency. Also working in conjunction with the receive path is
an offset correction circuit. These blocks are discussed in detail
in the following sections. Note that the power consumption of
the RxPGA can be modified via Reg. 0x13 as discussed in the
Power Control and Dissipation section.
Rev. 0 | Page 33 of 48
0
0 = 1dB
–6 TO 18dB
= 6dB
–6 TO 24dB
= 6dB
XTAL
RX–
4
6
10/12
REGISTER
CLK
SYN.
ADC
80MSPS
CLKOUT_1
CLKOUT_2
OSCIN
RX+
2
M
CLK
MULTIPLIER
2-POLE
LPF
1-POLE
LPF
SPORT
PGA[5:0]
RXCLK
RXEN/SYNC
ADIO[11:6]/
Tx[5:0]
ADIO[11:6]/
Rx[5:0]
GAIN
MAPPING
LUT
SPGA
AD9865/AD9866
Figure 68. Functional Block Diagram of Rx Path
RX PROGRAMMABLE GAIN AMPLIFIER
The RxPGA has a digitally programmable gain range from
12 dB to +48 dB with 1 dB resolution via a 6-bit word. Its
purpose is to extend the dynamic range of the Rx path such that
the input of the ADC is presented with a signal that scales
within its fixed 2 V input span. There are multiple ways of
setting the RxPGA’s gain as discussed in the RxPGA Control
section, as well as an alternative 3-bit gain mapping having a
range of 12 dB to +36 dB with 8 dB resolution.
The RxPGA is comprised of two sections: a continuous time
PGA (CPGA) for course gain and a switched capacitor PGA
(SPGA) for fine gain resolution. The CPGA consists of two
cascaded gain stages providing a gain range from 12 dB to
+42 dB with 6 dB resolution. The first
stage features a low noise
preamplifier (< 3.0 nV/rtHz), thereby eliminating the need for
an external preamplifier. The SPGA provides a gain range from
0 dB to 6 dB with 1 dB resolution. A look-up table (LUT) is used
to select the appropriate gain setting for each stage.
The nominal differential input impedance of the RxPGA input
appearing at the device RX+ and RX input pins is 400 //4 pF
(±20%) and remains relatively independent of gain setting. The
PGA input is self-biased at a 1.3 V common-mode level allow-
ing maximum input voltage swings of ±1.5 V at RX+ and RX.
AC coupling the input signal to this stage via coupling capaci-
tors (0.1 μF) is recommended
to ensure that any external dc
offset does not get amplified with high RxPGA gain settings,
potentially exceeding the ADC input range.
To limit the RxPGA’s self-induced input offset, an offset
cancellation loop is included. This cancellation loop is
automatically performed upon power-up and can also be
initiated via SPI. During calibration, the RxPGA’s first stage is
internally shorted, and each gain stage set to a high gain setting.
A digital servo loop slaves a calibration DAC, which forces the
Rx input offset to be within ±32 LSB for this particular high
gain setting. Although the offset varies for other gain settings,
the offset is typically limited to ±5% of the ADC’s 2 V input
span. Note that the offset cancellation circuitry is intended to
reduce the voltage offset attributed to only the RxPGA’s input
stage, not any dc offsets attributed to an external source.
The gain of the RxPGA should be set to minimize clipping of
the ADC while utilizing most of its dynamic range. The
maximum peak-to-peak differential voltage that does not result
in clipping of the ADC is shown in Figure 69. While the graph
suggests that maximum input signal for a gain setting of 12 dB
is 8.0 V p-p, the maximum input voltage into the PGA should
be limited to less than 6 V p-p to prevent turning on ESD
protection diodes. For applications having higher maximum
input signals, consider adding an external resistive attenuator
network. While the input sensitivity of the Rx path is degraded
by the amount of attenuation on a dB-to-dB basis, the low noise
characteristics of the RxPGA provide some design margin such
that the external line noise remains the dominant source.
0
GAIN (dB)
F
–12
–6
0
6
12
18
24
30
36
42
48
8.0000
4.0000
2.0000
1.0000
0.5000
0.2500
0.1250
0.0625
0.0312
0.0156
0.0100
Figure 69. Maximum Peak-to-Peak Input vs. RxPGA Gain Setting
that Does Not Result in ADC Clipping
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|---|---|
| AD9866BCP | Broadband Modem Mixed Signal Front End |
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| AD9870EB | IF Digitizing Subsystem |
| AD9873 | Analog Front End Converter for Set-Top Box, Cable Modem |
| AD9873-EB | Analog Front End Converter for Set-Top Box, Cable Modem |
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