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| 型號(hào)： | AD9866-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | 寬帶調(diào)制解調(diào)器混合信號(hào)前端 |
| 文件頁(yè)數(shù)： | 41/48頁(yè) |
| 文件大小： | 1647K |
| 代理商： | AD9866-EB |
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AD9866
Because the CPGA processes signals in the continuous time
domain, its performance versus bias setting remains mostly
independent of the sample rate. Table 25 shows how the typical
current consumption seen at AVDD (Pins 35 and 40) varies as a
function of Bits (7:5), while the remaining bits are maintained at
their default setting of 0. Only four of the possible settings result
in any reduction in current consumption relative to the default
setting. Reducing the bias level typically results in a degradation
in the THD versus frequency performance as shown in
Figure 80 due to a reduction of the amplifier’s unity gain
bandwidth, while the SNR performance remains relatively
unaffected.
Rev. 0 | Page 41 of 48
0
CPGA BIAS SETTING-BITS (7:5)
S
T
000
100
010
011
001
65.0
40.0
–20
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
42.5
45.0
47.5
50.0
52.5
55.0
57.5
60.0
62.5
SNR_RxPGA = 0dB
SNR_RxPGA = 36dB
THD_RxPGA = 0dB
THD_RxPGA = 36dB
Figure 80. THD vs. f
IN
Performance and RxPGA Bias Settings (000,001,010,100
with RxPGA = 0 and +36 dB and AIN = 1 dBFS, LPF set to 26 MHz
and f
ADC
= 50 MSPS)
Table 25. Analog Supply Current vs. CPGA Bias Settings at
f
ADC
= 65 MSPS
Bit 7
Bit 6
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Bit 5
0
1
0
1
0
1
0
1
mA
0
27
42
51
55
27
69
27
The SPGA is implemented as a switched capacitor amplifier.
Therefore, its performance versus bias level is mostly dependent
on the sample rate. Figure 81 shows how the typical current
consumption seen at AVDD (Pins 35 and 40) varies as a
function of bits (4:3) and sample rate, while the remaining bits
are maintained at their default setting of 0. Figure 81 shows how
the SNR and THD performance is affected for a 10 MHz sine
wave input as the ADC sample rate is swept from 20 MHz to 80
MHz.
0
ADC SAMPLE RATE (MSPS)
I
A
20
30
40
50
60
70
80
210
170
175
180
185
190
195
200
205
01
00
10
11
Figure 81. AVDD Current vs. SPGA Bias Setting and Sample Rate
0
SAMPLE RATE (MSPS)
S
T
20
80
30
70
40
50
60
65
55
–54
–74
–72
–70
–68
–66
–64
–62
–60
–58
–56
56
57
58
59
60
61
62
63
64
SNR-00
SNR-01
SNR-10
SNR-11
THD-00
THD-01
THD-10
THD-11
Figure 82. SNR and THD Performance vs. f
ADC
and SPGA Bias Setting with
RxPGA = 0 dB, f
IN
= 10 MHz. AIN =
1 dBFS
The ADC is based on a pipeline architecture with each stage
consisting of a switched capacitor amplifier. Therefore, its
performance versus bias level is also mostly dependent on the
sample rate. Figure 83 shows how the typical current consump-
tion seen at AVDD (Pins 35 and 40) varies as a function of bits
(2:0) and sample rate, while the remaining bits are maintained
at their default setting of 0. Setting Bit 4 or Reg. 0x07 corre-
sponds to the 011 setting, and the settings of 101 and 111 result
in higher current consumption. Figure 84 shows how the SNR
and THD performance are affected for a 10 MHz sine wave
input for the lower power settings as the ADC sample rate is
swept from 20 MHz to 80 MHz.
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