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參數資料
| 型號： | AD9876BSTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數： | 19/24頁 |
| 文件大小： | 666K |
| 代理商： | AD9876BSTRL |
REV. A
AD9876
–19–
source. Inverting CLK-A would affect the Tx sampling edge as
well as the Rx sampling edge.
The first nibble of each word can be read in as the least signifi
cant
nibble by setting the Rx LS Nibble First Bit (Register 8, Bit 2).
Also, the Rx path can be used in a Reduced Resolution Mode
by setting the Rx Port Multiplexer Bypass Bit (Register 8, Bit
0). In this mode, the Rx data-word becomes six bits and is read
in a single cycle. The Clocking Modes are the same as described
above, but the level of Rx SYNC will stay low.
The Rx [5:0] pins can be put into a high impedance state by
setting the Three-State Rx Port Bit (Register 8, Bit 3).
SERIAL INTERFACE FOR REGISTER CONTROL
The serial port is a 3-wire serial communications port consisting of
a clock (SCLK), chip select (
SENABLE
), and a bidirectional
data (SDATA) signal. The interface allows read/write access to
all registers that configure the AD9876 internal parameters. Single
or multiple byte transfers are supported as well as MSB first or
LSB first transfer formats.
General Operation of the Serial Interface
Serial communication over the serial interface can be from 1 to
5 bytes in length. The first byte is always the instruction byte.
The instruction byte establishes whether the communication is
going to be a read or write access, the number of data bytes to
be transferred, and the address of the first register to be accessed.
The instruction byte transfer is complete immediately upon the
8th rising edge of SCLK after
SENABLE
is asserted. Likewise,
the data registers change
immediately
upon writing to the 8th bit
of each data byte.
Instruction Byte
The instruction byte contains the following information as
shown below.
Table II. Instruction Byte Information
Bit I7 – R/W
This bit determines whether a read or a write data transfer will
occur after the instruction byte write. Logic high indicates read
operation; logic zero indicates a write operation.
Bits I6:I5 – N1:N0
These two bits determine the number of bytes to be transferred
during the data transfer cycle. The bit decodes are shown in the
table below.
Table III. Decode Bits
N1:N0
Description
0:0
0:1
1:0
1:1
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
Bits I4:I0 – A4:A0
These bits determine which register is accessed during the data
transfer portion of the communications cycle. For multibyte
transfers, this address is the starting byte address. The remain-
ing register addresses are generated by the AD9876/AD9875.
Serial Interface Port Pin Description
SCLK—Serial Clock
The serial clock pin is used to synchronize data transfers to and
from the AD9876 and to run the internal state machines. SCLK
maximum frequency is 25 MHz. All data transmitted to the
AD9876 is sampled on the rising edge of SCLK. All data read
from the AD9876 is validated on the rising edge of SCLK and is
updated on the falling edge.
SENABLE
—Serial Interface Enable
The
SENABLE
pin is active low. It enables the serial communi-
cation to the device.
SENABLE
select should stay low during
the entire communication cycle. All input on the serial port is
ignored when
SENABLE
is inactive.
SDATA—Serial Data I/O
The signal on this line is sampled on the first eight rising edges
of SCLK after
SENABLE
goes active. Data is then read from or
written to the AD9876 depending on what was read.
Figures 8 and 9 show the timing relationships between the three
SPI signals.
SENABLE
SCLK
SDATA
t
DH
t
DS
t
DS
t
PWH
t
SCLK
t
PWL
INSTRUCTION BIT 7
INSTRUCTION BIT 6
Figure 8. Timing Diagram Register Write to AD9876
SENABLE
SCLK
SDATA
DATA BIT n
DATA BIT n–1
t
DV
Figure 9. Timing Diagram Register Read from AD9876
MSB/LSB Transfers
The AD9876 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. The
bit order is controlled by the SPI LSB First Bit (Register 0, Bit
6). The default value is 0, MSB first. Multibyte data transfers in
MSB format can be completed by writing an instruction byte
that includes the register address of the last address to be accessed.
The AD9876 will automatically decrement the address for each
successive byte required for the multibyte communication cycle.
When the SPI LSB First Bit (Register 0, Bit 6) is set high, the
serial port interprets both instruction and data bytes LSB first.
Multibyte data transfers in LSB format can be completed by
writing an instruction byte that includes the register address of
B
S
M
B
S
L
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
I
W
/
R
1
N
0
N
4
A
3
A
2
A
1
A
0
A
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9876EB | 制造商:Analog Devices 功能描述: |
| AD9876-EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9877 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Mixed-Signal Front End Set-Top Box, Cable Modem |
| AD9877ABS | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9877ABS-1 | 制造商:Analog Devices 功能描述: |
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