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參數資料
| 型號： | AD9876BSTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數： | 3/24頁 |
| 文件大小： | 666K |
| 代理商： | AD9876BSTRL |
REV. A
–3–
AD9876
Test
Level
Parameter
Temp
Min
Typ
Max
Unit
Rx PATH GAIN/OFFSET
Minimum Programmable Gain
Maximum Programmable Gain (12 MHz Filter)
Maximum Programmable Gain (26 MHz Filter)
Gain Step Size
Gain Step Accuracy
Gain Range Error
Offset Error, PGA Gain = 0 dB
Absolute Gain Error
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
III
III
III
III
III
III
III
III
–6
36
30
2
±
0.4
±
1.0
±
10
±
0.8
dB
dB
dB
dB
dB
dB
LSB
dB
Rx PATH INPUT CHARACTERISTICS
Input Voltage Range
Input Capacitance
Differential Input Resistance
Input Bandwidth (–3 dB)
Input Referred Noise (at –36 dB Gain with Filter)
Input Referred Noise (at –6 dB Gain with Filter)
Common-Mode Rejection
Rx PATH LPF (Low Cutoff Frequency)
Cutoff Frequency
Cutoff Frequency Variation
Attenuation @ 22 MHz
Pass-Band Ripple
Group Delay Variation
Settling Time
(to 1% FS, Min to Max Gain Change)
Total Harmonic Distortion at Max Gain (THD)
Rx PATH LPF (High Cutoff Frequency)
Cutoff Frequency
Cutoff Frequency Variation
Attenuation @ 44 MHz
Pass-Band Ripple
Group Delay Variation
Settling Time
(to 1% FS, Min to Max Gain Change)
Total Harmonic Distortion at Max Gain (THD)
Rx PATH DIGITAL HPF
Latency (ADC Clock Source Cycles)
Roll-Off in Stop Band
–3 dB Frequency
Full
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
III
III
III
III
III
III
III
4
4
270
50
16
684
40
Vppd
pF
MHz
μ
V rms
μ
V rms
dB
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
III
III
III
III
III
12
±
7
20
±
1.0
30
MHz
%
dB
dB
ns
25
°
C
25
°
C
III
III
150
–68
ns
dBc
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
III
III
III
III
III
26
±
7
20
±
1.2
15
MHz
%
dB
dB
ns
25
°
C
25
°
C
III
III
80
–65
ns
dBc
Full
Full
Full
II
II
II
1
6
f
ADC
/400
Cycle
dB/Octave
Hz
Rx PATH DISTORTION PERFORMANCE
IMD: f1 = 6.5 MHz, f2 = 7.7 MHz
12 MHz Filter: 0 dB Gain
: 30 dB Gain
26 MHz Filter: 0 dB Gain
: 30 dB Gain
25
°
C
25
°
C
25
°
C
25
°
C
III
III
III
III
–65
–57
–65
–56
dBc
dBc
dBc
dBc
POWER-DOWN/DISABLE TIMING
DAC I
OUT
OFF after Tx QUIET Asserted
DAC I
ON after Tx QUIET De-Asserted
Power-Down Delay (Active to Power-Down)
DAC
Interpolator
Power-Up Delay (Power-Down to Active)
DAC
PLL
ADC
PGA
LPF
Interpolator
VRC
Minimum RESET Pulsewidth Low (t
RL
)
Full
Full
II
II
200
1
ns
μ
s
Full
Full
II
II
400
200
ns
ns
Full
Full
Full
Full
Full
Full
Full
Full
II
II
II
II
II
II
II
II
40
10
1000
1
1
200
2
5
μ
s
μ
s
μ
s
μ
s
μ
s
ns
μ
s
f
OSCIN
Cycles
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