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參數資料
| 型號： | AD9882KST-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Dual Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, MS-026BED, LQFP-100 |
| 文件頁數： | 16/36頁 |
| 文件大小： | 370K |
| 代理商： | AD9882KST-100 |
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REV. A
–16–
AD9882
Table V. VCO Frequency Ranges
PV1
PV0
Pixel Clock Range (MHz)
0
0
1
0
1
0
12
–
41
41
–
82
82
–
140
3. The 3-bit Charge Pump Current Register (Register 03H,
Bits 3
–
5). This register allows the current that drives the
low-pass loop filter to be varied. The possible current values
are listed in Table VI.
Table VI. Charge Pump Current/Control Bits
Ip2
Ip1
Ip0
Current (
m
A)
50
100
150
250
350
500
750
1500
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4. The 5-bit Phase Adjust Register (Register 04H, Bits 3
–
7).
The phase of the generated sampling clock may be shifted to
locate an optimum sampling point within a clock cycle. The
Phase Adjust Register provides 32 phase-shift steps of 11.25
∞
each. The Hsync signal with an identical phase shift is available
through the HSOUT pin.
The PLL characteristics are determined by the loop filter design,
the PLL charge pump current, and the VCO range setting.
The loop filter design is illustrated in Figure 6. Recommended
settings of VCO range and charge pump current for VESA
standard display modes are listed in Table VII.
P
VD
C
0.082 F
R
2.74k
C
P
0.0082 F
FILT
Figure 6. PLL Loop Filter Detail
Four programmable registers are provided to optimize the
performance of the PLL. These registers are:
1. The 12-bit Divisor Register (Registers 01H and 02H). The
input Hsync frequencies range from 15 kHz to 110 kHz. The
PLL multiplies the frequency of the Hsync signal, producing
pixel clock frequencies in the range of 12 MHz to 140 MHz.
The Divisor Register controls the exact multiplication factor.
This register may be set to any value between 221 and 4095.
(The divide ratio that is actually used is the programmed
divide ratio plus one.)
2. The 2-bit VCO Range Register (Register 03H, Bits 6 and 7).
To improve the noise performance of the AD9882, the VCO
operating frequency range is divided into three overlapping
regions. The VCO Range register sets this operating range.
The frequency ranges for the lowest and highest regions are
shown in Table V.
Table VII. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Refresh
Resolution
640
￥
480
Horizontal
Rate (Hz)
Standard
Frequency (kHz)
Pixel Rate (MHz)
VCORNGE
CURRENT
VGA
60
72
75
85
56
60
72
75
85
60
70
75
80
85
60
75
31.5
37.7
37.5
43.3
35.1
37.9
48.1
46.9
53.7
48.4
56.5
60.0
64.0
68.3
64.0
80.0
25.175
31.500
31.500
36.000
36.000
40.000
50.000
49.500
56.250
65.000
75.000
78.750
85.500
94.500
108.000
135.000
00
00
00
00
00
00
01
01
01
01
01
01
10
10
10
11
101
101
101
110
101
110
101
101
101
101
110
110
101
101
101
110
SVGA
800
￥
600
XGA
1024
￥
768
SXGA
1280
￥
1024
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9882KST-140 | 制造商:Analog Devices 功能描述:Interface for Flat Panel Display 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:LOW COST DUAL INTERFACE - Bulk 制造商:Analog Devices 功能描述:IC DUAL INTERFACE |
| AD9882KSTZ-100 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9882KSTZ-140 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9883 | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS Analog Interface for Flat Panel Displays |
| AD9883/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS Analog Interface for Flat Panel Displays |
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