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參數(shù)資料
| 型號： | AD9882KST-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Dual Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, MS-026BED, LQFP-100 |
| 文件頁數(shù)： | 27/36頁 |
| 文件大小： | 370K |
| 代理商： | AD9882KST-100 |
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REV. A
AD9882
–27–
Active HIGH means the leading edge of the Hsync pulse is
positive-going. This means that timing will be based on the
leading edge of Hsync, which is now the RISING edge.
The device will operate if this bit is set incorrectly, but the inter-
nally generated clamp position, as established by Clamp Placement
(Register 05H), will not be placed as expected, which may
generate clamping errors.
The power-up default value is HSPOL = 1.
10
5
Hsync Output Polarity
One bit that determines the polarity of the Hsync output and the
SOG output. Table XVI shows the effect of this option. SYNC
indicates the logic state of the sync pulse.
Table XVI. Hsync Output Polarity Settings
Setting
SYNC
0
1
Logic 1 (positive polarity)
Logic 0 (negative polarity)
The default setting for this register is 0.
10
This bit is used to override the automatic Hsync selection. To
override, set this bit to logic 1. When overriding, the active
Hsync is set via Bit 3 in this register.
4
Active Hsync Override
Table XVII. Active Hsync Override Settings
Override
Result
0
1
Autodetermine the active Hsync.
Override. Bit 3 determines the active Hsync.
The default for this register is 0.
10
This bit is used under two conditions. It is used to select the active
Hsync when the override bit is set (Bit 4). Alternately, it is used
to determine the active Hsync when not overriding, but both
Hsyncs are detected.
3
Active Hsync Select
Table XVIII. Active Hsync Select Settings
Select
Result
0
1
Hsync input
Sync-on-Green input
The default for this register is 0.
10
One bit that determines the polarity of the Vsync output.
Table XIX shows the effect of this option. SYNC indicates the
logic state of the sync pulse.
2
Vsync Output Polarity
Table XIX. Vsync Output Polarity Settings
Setting
SYNC
1
0
Not invert
Invert
The default setting for this register is 0.
10
This bit is used to override the automatic Vsync selection. To
override, set this bit to logic 1. When overriding, the active
interface is set via Bit 0 in this register.
1
Active Vsync Override
Table XX. Active Vsync Override Settings
Override
Result
0
1
Autodetermine the active Vsync
Override. Bit 0 determines the active Vsync.
The default for this register is 0.
10
This bit is used to select the active Vsync when the override bit
is set (Bit 1).
0
Active Vsync Select
Table XXI. Active Vsync Select Settings
Select
Result
0
1
Vsync input
Sync separator output
The default for this register is 0.
11
A bit that enables/disables clamping.
7
Clamp Function
Table XXII. Clamp Input Signal Source Settings
Clamp Function
Function
0
1
Internally generated clamp enabled
Clamping disabled
A 0 enables the clamp timing circuitry controlled by clamp
placement and clamp duration. The clamp position and duration
is counted from the trailing edge of Hsync.
A 1 disables clamping. The three channels are clamped when
the CLAMP signal is active.
Power-up default value is CLAMP FUNCTION = 0.
11
A bit that determines whether the RED channel is clamped to
ground or to midscale. For RGB video, all three channels are
referenced to ground. For YPbPr, the Y channel is referenced
to ground, but the PbPr channels are referenced to midscale.
Clamping to midscale actually clamps to Pin 74.
6
RED Clamp Select
Table
XXIII.
RED Clamp Select Settings
Clamp
Function
0
1
Clamp to ground
Clamp to midscale (Pin 74)
The default setting for this register is 0.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9882KST-140 | 制造商:Analog Devices 功能描述:Interface for Flat Panel Display 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:LOW COST DUAL INTERFACE - Bulk 制造商:Analog Devices 功能描述:IC DUAL INTERFACE |
| AD9882KSTZ-100 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9882KSTZ-140 | 功能描述:IC INTERFACE/DVI 100MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9883 | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS Analog Interface for Flat Panel Displays |
| AD9883/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS Analog Interface for Flat Panel Displays |
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