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參數資料
| 型號： | AD9882KST-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Dual Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, MS-026BED, LQFP-100 |
| 文件頁數： | 23/36頁 |
| 文件大小： | 370K |
| 代理商： | AD9882KST-100 |
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REV. A
AD9882
–23–
Table IX. Control Register Map (continued)
Hex
Address
Read and Write
or Read Only
Default
Value
Bit
Register Name
Function
10
R/W
7
0
***
****
Hsync Polarity Override
0 = Polarity determined by chip
1 = Polarity set by 10H, Bit 6
0 = Active low polarity
1 = Active high polarity
0 = Active high sync signal
1 = Active low sync signal
0 = No override
1 = User overrides, analog Hsync set by 10H, Bit 3
0 = Analog Hsync from the Hsync input pin
1 = Analog Hsync from SOG
This bit is used if Register 10H, Bit 4 is set to
1 or if both syncs are active.
0 = Invert
1 = Not inverted
0 = No override
1 = User overrides, analog Vsync set by 10H, Bit 0
0 = Analog Vsync from the Vsync input pin
1 = Analog Vsync from sync separator
0 = Clamping with internal clamp
1 = Clamping disabled
0 = Clamp to ground
1 = Clamp to midscale for red channel
0 = Clamp to ground
1 = Clamp to midscale for green channel
0 = Clamp to ground
1 = Clamp to midscale for blue channel
0 = Disabled coast
1 = Coasting with internally generated coast signal
0 = Coast polarity determined by the chip
1 = Coast polarity set by 11H, Bit 1
This bit must be set to 1 to disable coast.
0 = Active low coast signal
1 = Active high coast signal
This bit must be set to 1 to disable coast.
Number of Hsync periods that coast goes active
prior to Vsync.
Number of Hsync periods before coast goes inactive
following Vsync.
6
*
1
**
****
Input Hsync Polarity
5
**
0
*
****
Output Hsync Polarity
4
***
0
****
Active Hsync Override
3
****
0
***
Active Hsync Select
2
****
*
0
**
Output Vsync Polarity
1
****
**
0
*
Active Vsync Override
0
****
***
0
Active Vsync Select
11
R/W
7
0
***
****
Clamp Function
6
*
0
**
****
Red Clamp Select
5
**
0
*
****
Green Clamp Select
4
***
0
****
Blue Clamp Select
3
****
1
***
Coast Select
2
****
*
0
**
Coast Polarity Override
1
****
**
1
*
Input Coast Polarity
12
R/W
7
–
0
0000 0000
Pre-Coast
13
R/W
7
–
0
0000 0000
Post-Coast
14
R/W
7
–
6
11
**
****
Output Drive Select
Selects among high, medium, and low output
drive strength.
0 = Low bandwidth of 10 MHz
1 = High bandwidth of 300 MHz
0 = DVI data clock output not inverted
1 = DVI data clock output inverted
For digital interface only.
0 = Normal outputs
1 = High impedance outputs
Address Bit 0 = 0 for HDCP Slave Port
Address Bit 1 = 1 for HDCP Slave Port
0 = Full chip power-down
5
**
1
*
****
Programmable Bandwidth
4
***
0
****
DVI Clock Invert
3
****
0
***
DVI PDO Three-State
2
****
*
0
**
HDCP Address
1
****
**
1
*
Power-Down
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