- 您現在的位置：買賣IC網 > PDF目錄373971 > AD9937 (Analog Devices, Inc.) CCD Signal Processor with Precision Timing⑩ Generator PDF資料下載
參數資料
| 型號： | AD9937 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing⑩ Generator |
| 中文描述： | CCD信號處理器精確定時⑩發生器 |
| 文件頁數： | 25/44頁 |
| 文件大小： | 410K |
| 代理商： | AD9937 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
REV. 0
AD9937
–25–
MASTER AND SLAVE MODE OPERATION
The AD9937 defaults at power up into slave mode operation.
During slave mode operation, the VD and HD pins are config-
ured as inputs for external VD and HD signals. The AD9937
can be configured into master mode operation to output the
VD and HD signals by programming MASTER = 1 (control
addr 0x05).
HORIZONTAL AND VERTICAL TIMING
The internal VD and HD synchronization timing is configured
by using the registers in Table X. As shown in Figure 17, the
HD and VD clock positions are referenced to the 12-bit
H-counter and 11-bit V-counter, respectively. This allows for
a maximum of 4096 horizontal pixels by 2048 vertical
line resolution.
The AD9937 provides programmability for two HD pulses per
line with the ability to independently set the last line length by
using the HDLASTLEN register (Mode_Reg(4)). Additionally,
the HDLENx (where x = 0, 1, 2, 3, 4 representing CCD regions)
registers can be used to set different line lengths for each CCD
region. As shown in Figure 31, up to five unique CCD regions
may be specified.
Individual HMASK Sequence
The HMASK programmable timing shown in Figure 18 pro-
vides two HMASK toggle positions and an H1MASK polarity
setting. These registers can be used to disable the horizontal
H1 and H2 outputs during the vertical transfer period. As shown
in Figure 18, the H2(A, B) outputs are always the opposite
polarity of the H1(A
–
D) outputs. The H1MASKSTART and
H1MASKSTOP registers reference the 11-bit VD counter.
Individual PBLK Sequences
Up to two individual PBLK pulses can be programmed per line
using the registers in Table XI. During the time PBLK is active,
the DOUT[9:0] data is fixed at the level set in the PBLK_LEVEL
(control addr 0x03) register. Figures 19, 20, and 21 provide
examples of PBLK registers described in Table XI.
Table X. HD and VD Registers
Length
(Bits)
Register Name
Register Type
Range
Description
VDLEN
VDTOG1
VDTOG2
HDTOG1
HDTOG2
HDTOG3
HDTOG4
HDLASTLEN
HDLEN0
HDLEN1
HDLEN2
HDLEN3
HDLEN4
VDHD_INVERT
11
4
4
12
12
12
12
12
12
12
12
12
12
1
Mode_Reg(4)
Mode_Reg(4)
Mode_Reg(4)
Mode_Reg(2)
Mode_Reg(2)
Mode_Reg(3)
Mode_Reg(3)
Mode_Reg(4)
Mode_Reg(15)
Mode_Reg(16)
Mode_Reg(17)
Mode_Reg(18)
Mode_Reg(19)
Control 0x04
0
–
2047 Line Number
0
–
15 Pixel Location
0
–
15 Pixel Location
0
–
4095 Pixel Location
0
–
4095 Pixel Location
0
–
4095 Pixel Location
0
–
4095 Pixel Location
0
–
4095 Pixel Location
0
–
4095 Pixel Location
0
–
4095 Pixel Location
0
–
4095 Pixel Location
0
–
4095 Pixel Location
0
–
4095 Pixel Location
HIGH/LOW
11-Bit VD Counter Length
VD Toggle Position 1. See Figure 17.
VD Toggle Position 2. See Figure 17.
HD Toggle Position 1. See Figure 17.
HD Toggle Position 2. See Figure 17.
HD Toggle Position 3. See Figure 17.
HD Toggle Position 4. See Figure 17.
HD Last Line Length. See Figure 17.
12-Bit HD Counter Length Value for CCD Region 0
12-Bit HD Counter Length Value for CCD Region 1
12-Bit HD Counter Length Value for CCD Region 2
12-Bit HD Counter Length Value for CCD Region 3
12-Bit HD Counter Length Value for CCD Region 4
VD and HD Inversion Control
相關PDF資料 |
PDF描述 |
|---|---|
| AD9937KCP | CCD Signal Processor with Precision Timing⑩ Generator |
| AD9937KCPRL | TVPS00RF-25-35PB W/ PC CONTACT |
| AD9942 | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9942BBCZ | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9942BBCZRL | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9937BCPZ-24 | 制造商:Analog Devices 功能描述: |
| AD9937BCPZ-27 | 功能描述:IC CCD SIGNAL PROC/GEN 制造商:analog devices inc. 系列:* 零件狀態:上次購買時間 標準包裝:1 |
| AD9937BCPZRL-24 | 制造商:Analog Devices 功能描述: |
| AD9937BCPZRL-27 | 功能描述:IC CCD SIGNAL PROC/GEN 制造商:analog devices inc. 系列:* 零件狀態:上次購買時間 標準包裝:1 |
| AD9937KCP | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 56-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發布緊急采購，3分鐘左右您將得到回復。