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參數資料
| 型號： | AD9937 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Precision Timing⑩ Generator |
| 中文描述： | CCD信號處理器精確定時⑩發生器 |
| 文件頁數： | 33/44頁 |
| 文件大小： | 410K |
| 代理商： | AD9937 |
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REV. 0
AD9937
–33–
MASKING H1 AND H2 OUTPUTS
The H1 and H2 outputs can be masked during the horizontal
and vertical transfers as shown in Figures 29 and 30.
Horizontal Masking
The H1 clocks are masked with the polarity set by the
H1MASKPOL register as shown in Figure 29. The H2 outputs
will always be the opposite polarity of H1. The H1 and H2 out-
puts are masked from HDLEN + 1 to HBLKTOG1 position
when HDLASTLEN is the same as HDLEN. In the case when
HDLASTLEN is greater than HDLEN, the H1 and H2 outputs
will be masked during the entire last line. It is recommended to
always program HBLKTOG3 and HBLKTOG4 to 4095 when
only one H-blanking in a line is required. It is also recommended
to program HBLKTOG1 < HBLKTOG2 < HBLKTOG3 <
HBLKTOG4.
Vertical Masking
As shown in Figure 30, the H1 and H2 outputs remain masked
if the horizontal HMASK is followed by the vertical HMASK
region or if the vertical HMASK region is followed by the hori-
zontal HMASK region.
Table XVI. Special H Pattern Registers
Length
(Bits)
Register
Type
Register Name
HBLKTOG1
1
HBLKTOG2
1
HBLKTOG3
1
HBLKTOG4
1
H1APOL
H1BPOL
H1CPOL
H1DPOL
H2APOL
H2BPOL
SPHSTART0
2
SPHSTART1
2
SPH1A1
SPH1B1
SPH1C1
SPH1D1
SPH2A1
SPH2B1
SPH1A2
SPH1B2
SPH1C2
SPH1D2
SPH2A2
SPH2B2
SPH1A3
SPH1B3
SPH1C3
SPH1D3
SPH2A3
SPH2B3
SPHEN0
SPHEN1
SPHEN2
SPHEN3
SPHEN4
Range
Description
12
12
12
12
1
1
1
1
1
1
8
8
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
1
1
1
1
1
Mode_Reg(7)
Mode_Reg(7)
Mode_Reg(8)
Mode_Reg(8)
HLM_Reg(1)
HLM_Reg(1)
HLM_Reg(1)
HLM_Reg(1)
HLM_Reg(1)
HLM_Reg(1)
HLM_Reg(8)
HLM_Reg(9)
HLM_Reg(2)
HLM_Reg(2)
HLM_Reg(2)
HLM_Reg(3)
HLM_Reg(3)
HLM_Reg(3)
HLM_Reg(4)
HLM_Reg(4)
HLM_Reg(4)
HLM_Reg(5)
HLM_Reg(5)
HLM_Reg(5)
HLM_Reg(6)
HLM_Reg(6)
HLM_Reg(6)
HLM_Reg(7)
HLM_Reg(7)
HLM_Reg(7)
Mode_Reg(15)
Mode_Reg(16)
Mode_Reg(17)
Mode_Reg(18)
Mode_Reg(19)
0
–
4095 Pixel Locations
0
–
4095 Pixel Locations
0
–
4095 Pixel Locations
0
–
4095 Pixel Locations
High/Low
High/Low
High/Low
High/Low
High/Low
High/Low
0
–
255 Pixel Locations
0
–
255 Pixel Locations
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
6 Individual Bits
High/Low
High/Low
High/Low
High/Low
High/Low
HBLK Toggle Position 1
HBLK Toggle Position 2
HBLK Toggle Position 3
HBLK Toggle Position 4
H1A Special H Pattern Start Polarity
H1B Special H Pattern Start Polarity
H1C Special H Pattern Start Polarity
H1D Special H Pattern Start Polarity
H2A Special H Pattern Start Polarity
H2B Special H Pattern Start Polarity
LM Pattern #0 (LM0) Special H Pulse Start Position
LM Pattern #1 (LM1) Special H Pulse Start Position
H1A Special H Pattern during LM Repetition 1
H1B Special H Pattern during LM Repetition 1
H1C Special H Pattern during LM Repetition 1
H1D Special H Pattern during LM Repetition 1
H2A Special H Pattern during LM Repetition 1
H2B Special H Pattern during LM Repetition 1
H1A Special H Pattern during LM Repetition 2
H1B Special H Pattern during LM Repetition 2
H1C Special H Pattern during LM Repetition 2
H1D Special H Pattern during LM Repetition 2
H2A Special H Pattern during LM Repetition 2
H2B Special H Pattern during LM Repetition 2
H1A Special H Pattern during LM Repetition 3
H1B Special H Pattern during LM Repetition 3
H1C Special H Pattern during LM Repetition 3
H1D Special H Pattern during LM Repetition 3
H2A Special H Pattern during LM Repetition 3
H2B Special H Pattern during LM Repetition 3
Special H Pattern Enable in CCD Region 0
Special H Pattern Enable in CCD Region 1
Special H Pattern Enable in CCD Region 2
Special H Pattern Enable in CCD Region 3
Special H Pattern Enable in CCD Region 4
NOTES
1
The HBLKTOGx toggle positions reference the 12-bit HD counter.
2
The SPHSTART0 and SPHSTART1 toggle positions reference the 8-bit LM counter.
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