
REV. 0
–42–
AD9937
CIRCUIT LAYOUT INFORMATION
The AD9937 typical circuit connection is shown in Figure 41.
The PCB layout is critical in achieving good image quality from
the AD9937 product. All of the supply pins, particularly the
AVDD, DVDD, TCVDD, RSVDD, HVDD1, and HVDD2
supplies, must be decoupled to ground with good quality high
frequency chip capacitors. The decoupling capacitors should be
located as close as possible to the supply pins, and should have
a very low impedance path to a continuous ground plane. There
should also be a 4.7
μ
F or larger value bypass capacitor for each
main supply although this is not necessary for each individual pin.
In most applications, it is easier and recommended to share the
same supply for AVDD, DVDD, TCVDD, RSVDD, HVDD1,
and HVDD2, which may be done as long as the individual supply
pins are separately bypassed at each supply pin. A separate 3 V
supply should be used for DRVDD with this supply pin decoupled
to the same ground plane as the rest of the chip. A separate
ground for DRVSS is not recommended.
The analog bypass pins (REFB, REFT) should also be carefully
decoupled to ground as close as possible to their respective pins.
The analog input (CCDIN) capacitor should also be located
close to the pin.
The H1(A
–
D), H2(A, B), and RS printed circuit board traces
should be designed to have low inductance to avoid excessive distor-
tion of the signals. Heavier traces are recommended, because of
the large transient current demand on H1(A
–
D) and H2(A, B) by
the CCD. If possible, physically locate the AD9937 closer to the
CCD to reduce the inductance on these lines. As always, the rout-
ing path should be as direct as possible from the AD9937 to the
CCD. Careful trace impedance considerations must also be made
with applications using a flex printed circuit (FPC) connecting the
CCD to the AD9937. FPC trace impedances can be controlled
by applying a solid uniform ground plane under the H1(A
–
D),
H2(A, B), and RS traces. This helps minimize the amount of
overshoot and ringing on these signals at the CCD inputs.
36
35
34
33
32
31
30
29
37
39
38
42
41
40
15 16 17 18 19 20 21 22 23 24
25 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
48 47 46 45 44 43
PIN 1
IDENTIFIER
CCDIN
AVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
AD9937
(TOP VIEW
10
DATA
OUTPUTS
3V
ANALOG SUPPLY
3V
DRIVER
SUPPLY
DRVDD
DRVSS
REFB
REFT
AVSS
VCKM
TCVDD
TCVSS
NC
V
H
R
V1A/B
V
V
O
V
TG1A
L
D
D
H
H
SERIAL
INTERFACE
4.7 F
8
OFD, LM, V4, TG3B, V3A/B,
TG3A, V2, TG1B, V1A/B, TG1A,
TO V-DRIVER
0.1 F
0.1 F
0.1 F
0.1 F
50
51
52
53
54
55
56
49
NC
NC
6
DATA OUTPUT CLOCK
3V ANALOG SUPPLY
0.1 F
0.1 F
0.1 F
H
H
R
R
H
H
H
H
H
NC
NC
H1D, H2B, H1B, H1C, H2A, H1A
RS
REF CLOCK INPUT
TG1B
T
T
S
S
S
3
2
V
H
4.7 F
0.1 F
CCD SIGNAL
3V ANALOG SUPPLY
VD, HD
1.0 F
1.0 F
3V ANALOG SUPPLY
Figure 41. Typical Circuit Configuration