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參數(shù)資料
| 型號： | AD9957_07 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | 1 GSPS的正交數(shù)字上變頻器與18位智商數(shù)據(jù)路徑和14位DAC |
| 文件頁數(shù)： | 29/60頁 |
| 文件大小： | 840K |
| 代理商： | AD9957_07 |
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AD9957
RAM Bidirectional Ramp Mode
This mode is unique in that the RAM segment playback mode
word of both RAM segment registers must be programmed for
RAM bidirectional ramp mode.
Rev. 0 | Page 29 of 60
In bidirectional ramp mode, upon assertion of an I/O update,
the RAM readies for playback operation using the parameters
programmed into RAM Segment Register 0. The data is
delivered at the appropriate rate and to the destination as
specified by the RAM playback destination bit.
The playback rate is governed by the timer that is internal to the
RAM state machine, and its period (t) is determined by the state
of the RAM playback destination bit as detailed in the RAM
Playback Operation section.
Playback begins upon a 0 to 1 logic transition on the RT pin.
This instructs the state machine to increment through the
address range specified in RAM Segment Register 0 starting
with the start address. As long as the RT pin remains Logic 1,
the state machine continues to play back the RAM data until it
reaches the end address, at which point the state machine halts.
A Logic 1 to Logic 0 transition on the RT pin instructs the state
machine to switch to RAM Segment Register 1 and to decrement
through the address range starting with the end address. As
long as the RT pin remains Logic 0, the state machine continues
to play back the RAM data until it reaches the start address, at
which point the state machine halts.
It is important to note that RAM Segment Register 1 is played
back in reverse order for bidirectional ramp mode. This must be
kept in mind when the RAM contents are loaded via the serial
I/O port when bidirectional ramp is the intended playback mode.
A graphic representation of the bidirectional ramp mode
appears in Figure 44. It demonstrates the action of the state
machine in response to the RT pin. If the RT pin changes states
before the state machine reaches the programmed start or end
address, the internal timer is restarted and the direction of the
address counter reversed.
1
2
3
4
5
6
7
8
0
1
RAM SEGMENT
0
1
0
1
0
Δ
t
Δ
t
Δ
t
Δ
t
Δ
t
START ADDRESS NUMBER 1
START ADDRESS NUMBER 0
END ADDRESS NUMBER 1
END ADDRESS
NUMBER 0
RAM
ADDRESS
RAM
ADDRESS
RT
PIN
1 PDCLK CYCLE
OR
M DDS CLOCK CYCLES
I/O_UPDATE
Figure 44. Bidirectional Ramp Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9957BCPZ | 制造商:Analog Devices 功能描述:GSPS QUADRATURE DIGITAL UPCONVERTER W/18-BIT IQ DATA PATH - Trays |
| AD9957BSVZ | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9957BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9957BSVZREEL13 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9958 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs |
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