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參數(shù)資料
| 型號(hào)： | AD9957_07 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | 1 GSPS的正交數(shù)字上變頻器與18位智商數(shù)據(jù)路徑和14位DAC |
| 文件頁數(shù)： | 31/60頁 |
| 文件大小： | 840K |
| 代理商： | AD9957_07 |
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AD9957
Rev. 0 | Page 31 of 60
START ADDRESS
RAM
ADDRESS
END ADDRESS
1
1 PDCLK CYCLE
OR
M DDS CLOCK CYCLES
Δ
t
I/O_UPDATE OR
RT TRANSITION
2
3
1
Δ
t
0
Figure 45. Continuous Bidirectional Ramp Timing Diagram
RAM Continuous Bidirectional Ramp Mode
In continuous bidirectional ramp mode, upon assertion of an
I/O update or a state change on the RT pin, the RAM begins
playback operation using the parameters programmed into the
selected RAM segment register. Data is extracted from RAM
over the specified address range contained in the start address
and end address. The data is delivered at the appropriate rate
and to the destination as specified by the RAM playback
destination bit.
The playback rate is governed by the timer internal to the RAM
state machine and its period ( t) is determined by the state of
the RAM playback destination bit as detailed in the RAM
P
layback
O
peration section.
After initialization, the internal state machine begins extracting
data from the RAM at the start address of the active RAM
segment register and increments the address counter until it
reaches the end address, at which point the state machine
reverses the direction of the address counter and begins
decrementing through the address range. Whenever one of the
terminal addresses is reached, the state machine reverses the
address counter; the process continues indefinitely.
Note that a change in state of the RT pin aborts the current
waveform and the newly selected RAM segment register is used
to initiate a new waveform.
A graphic representation of the continuous bidirectional ramp
mode is shown in Figure 45. The circled numbers in Figure 45
indicate specific events, explained as follows:
Event 1—an I/O update or state change on the RT pin has
activated the RAM continuous bidirectional ramp mode. The
state machine initializes to the start address of the active RAM
segment register. The state machine begins incrementing
through the specified address range.
Event 2—the state machine reaches the end address of the active
RAM segment register.
Event 3—the state machine reaches the start address of the
active RAM segment register.
This action continues indefinitely until the next I/O update or
state change on the RT pin.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9957BCPZ | 制造商:Analog Devices 功能描述:GSPS QUADRATURE DIGITAL UPCONVERTER W/18-BIT IQ DATA PATH - Trays |
| AD9957BSVZ | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9957BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9957BSVZREEL13 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9958 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs |
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